Abstract: A triboelectric personal protective equipment (PPE) includes a first layer of a first triboelectric material; a second layer of a second triboelectric material; a circuit configured to store and transfer triboelectric charge generated from the first layer and the second layer; a third layer and a fourth layer connected to and powered by the circuit. The first triboelectric material and a second triboelectric material have a difference in triboelectric charge density (TECD) of at least 35 ?C/m2. The third layer and the fourth layer provide an electric field that is configured to electrify particles having a size of 10 nm to 10 ?m between the third layer and the fourth layer.

Abstract: A system for building, training and productionizing machine learning models is disclosed. A model training specification is received, and a plurality of sets of hyper-parameters is obtained. Sets of training data and hyper parameter sets are distributed to distributed training systems. Models are trained in parallel using different sets of training data. Models are trained using multiple sets of hyper parameters. A candidate hyper-parameter set is selected, based on a measure of estimated effectiveness of the trained predictive models, and a production predictive model is generated by training a predictive model using the selected candidate hyper-parameter set and the complete set of training data.

Abstract: A system for building, training and productionizing machine learning models is disclosed. A model training specification is received, and a plurality of sets of hyper-parameters is obtained. Sets of training data and hyper parameter sets are distributed to distributed training systems. Models are trained in parallel using different sets of training data. Models are trained using multiple sets of hyper parameters. A candidate hyper-parameter set is selected, based on a measure of estimated effectiveness of the trained predictive models, and a production predictive model is generated by training a predictive model using the selected candidate hyper-parameter set and the complete set of training data.

Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

Abstract: A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion, but electrically insulated from the first portion by a capacitor dielectric layer; (d) a second doped semiconductor region wrapping around the second portion, but electrically insulated from the second portion by a collar dielectric layer. The second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion. The collar dielectric layer is in direct physical contact with the capacitor dielectric layer. When going away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.

Abstract: A system in one embodiment includes a multiprocessor chip comprising a plurality of cores; a plurality of power circuits, each power circuit being coupled to one of the cores; and an electrically programmable fuse in each power circuit. Each electrically programmable fuse further comprises a first electrode coupled to the associated power circuit; a second electrode coupled to the associated power circuit; a first pad coupled to the first electrode; a second pad coupled to the second electrode; and an electrically conductive material extending between the first and second electrodes and forming part of the associated power circuit, the electrically conductive material being characterized as tending to electromigrate from one of the electrodes to the other electrode under an applied electrical current passing between the electrodes, wherein the electromigration increases an overall resistance of the power circuit.

Abstract: A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion, but electrically insulated from the first portion by a capacitor dielectric layer; (d) a second doped semiconductor region wrapping around the second portion, but electrically insulated from the second portion by a collar dielectric layer. The second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion. The collar dielectric layer is in direct physical contact with the capacitor dielectric layer. When going away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.

Abstract: A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.

Abstract: An integrated circuit including a dynamic random access memory (DRAM) array is disclosed herein in which a DRAM cell includes a storage capacitor within a deep trench, a transistor having a channel extending along a sidewall of the deep trench and a gate conductor within the deep trench, and a wordline contacting the gate conductor from above, wherein the wordline has a centerline which is offset from the centerline of the gate conductor. The DRAM cell further includes active area extending from the transistor channel, and a bitline contact to the active area which is bordered by an insulating spacer of the sidewall of the wordline.

Abstract: An integrated circuit including a dynamic random access memory (DRAM) array is disclosed herein in which a DRAM cell includes a storage capacitor within a deep trench, a transistor having a channel extending along a sidewall of the deep trench and a gate conductor within the deep trench, and a wordline contacting the gate conductor from above, wherein the wordline has a centerline which is offset from the centerline of the gate conductor. The DRAM cell-further includes active area extending from the transistor channel, and a bitline contact to the active area which is bordered by an insulating spacer of the sidewall of the wordline.

Abstract: A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.

Abstract: A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.

Abstract: An electronic array of data elements, in particular, a flat display device preferably of the PALC type in which the plasma channels are defined by walls of an organic material, preferably a polyimide material. A protective layer is provided over the polyimide walls to prevent deterioration. Spaced electrode portions are preferably provided on facing surfaces of the walls. The preferred method is to lay down a thick layer of polyimide material and a thin resist over the polyimide layer, pattern the resist, and then use the resist to pattern the polyimide layer in the shape of the desired walls. The walls are then covered with a thin dielectric sheet-like member to form the plasma channels.

Abstract: A channel member for a PALC panel has a channel in its surface and a wire in the channel as an electrode of the PALC panel.

Abstract: A high pressure gas discharge lamp and the method of making same utilizing integrated circuit fabrication techniques. The lamp is manufactured from heat and pressure resistant planar substrates in which cavities are etched, by integrated circuit manufacturing techniques, so as to provide a cavity forming the gas discharge tube. Electrodes are deposited in the cavity. The cavity is filled with gas discharge materials such as mercury vapor, sodium vapor or metal halide. The substrates are bonded together and channels may be etched in the substrate so as to provide a means for connection to the electrodes. Lamps having ignition enhancing and hot restrike features, as well as single-sided electrodes, are disclosed.

Abstract: A high pressure gas discharge lamp and the method of making same utilizing integrated circuit fabrication techniques. The lamp is manufactured from heat and pressure resistant planar substrates in which cavities are etched, by integrated circuit manufacturing techniques, so as to provide a cavity forming the gas discharge tube. Electrodes are deposited in the cavity. The cavity is filled with gas discharge materials such as mercury vapor, sodium vapor or metal halide. The substrates are bonded together and channels may be etched in the substrate so as to provide a means for connection to the electrodes. Electrodeless RF activated lamps may also be fabricated by this technique. Lamps fabricated from three or more planar substrates are disclosed.

Abstract: A process for fabricating the channel substrate of a plasma-addressed electro-optic display device comprising a layer of electro-optic material, data electrodes coupled to the electro-optic layer and adapted to receive data voltages for activating portions of the electro-optic layer, and a plurality of plasma channels extending generally transverse to the data electrodes for selectively switching on said electro-optic portions and closed off by a thin dielectric sheet, typically a thin glass sheet. The channel substrate is fabricated using anodic bonding to attach the thin glass sheet to an etched or walled preferably glass substrate containing the channels. This reduces stresses in the thin glass sheet. Reduced stress allows post processing of the thin sheet, particularly further etching to reduce its thickness.