Patents by Inventor Badredin Fatemizadeh
Badredin Fatemizadeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170346477Abstract: A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure, a dielectric layer at least partially disposed in a trench of the silicon semiconductor structure in a thickness direction, and a gate conductor embedded in the dielectric layer and extending into the trench in the thickness direction. The dielectric layer and the gate conductor are at least substantially symmetric with respect to a center axis of the trench extending in the thickness direction, as seen when the LDMOS transistor is viewed cross-sectionally in a direction orthogonal to the lateral and thickness directions.Type: ApplicationFiled: May 23, 2017Publication date: November 30, 2017Inventors: John Xia, Marco A. Zuniga, Badredin Fatemizadeh, Vijay Parthasarathy
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Publication number: 20170338731Abstract: A voltage regulator includes a high-side device, a low-side device, and a controller. The high-side device includes first and second transistors each coupled between an input terminal and an intermediate terminal, where the first transistor has a higher breakdown voltage than the second transistor. The low-side device is coupled between the intermediate terminal and a ground terminal. The controller is configured to drive the high-side and low-side devices to (a) alternately couple the intermediate terminal to the input terminal and the ground terminal and (b) cause the first transistor to control a voltage across the second transistor during switching transitions of the second transistor.Type: ApplicationFiled: July 28, 2017Publication date: November 23, 2017Inventors: Marco A. Zuniga, Chiteh Chiang, Yang Lu, Badredin Fatemizadeh, Amit Paul, Jun Ruan, Craig Cassella
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Publication number: 20170263766Abstract: A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure including (a) a base layer, (b) a p-type reduced surface field effect (RESURF) layer disposed over the base layer in a thickness direction, (c) a p-body disposed over the p-type RESURF layer in the thickness direction, (d) a source p+ region and a source n+ region each disposed in the p-body, (e) a high-voltage n-type laterally-diffused drain (HVNLDD) disposed adjacent to the p-body in a lateral direction orthogonal to the thickness direction, the HVNLDD contacting the p-type RESURF layer, and (f) a drain n+ region disposed in the HVNLDD. The LDMOS transistor further includes (a) a first dielectric layer disposed on the silicon semiconductor structure in the thickness direction over at least part of the p-body and the HVNLDD and (b) a first gate conductor disposed on the first dielectric layer in the thickness direction.Type: ApplicationFiled: March 13, 2017Publication date: September 14, 2017Inventors: John Xia, Marco A. Zuniga, Badredin Fatemizadeh
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Patent number: 9722483Abstract: A voltage regulator has an input terminal and a ground terminal. The voltage regulator includes a high-side device, a low side device, and a controller. The high-side device is coupled between the input terminal and an intermediate terminal. The high-side device includes first and second transistors each coupled between the input terminal and the intermediate terminal, such that the first transistor controls a drain-source switching voltage of the second transistor. The low-side device is coupled between the intermediate terminal and the ground terminal. The controller drives the high-side and low-side devices to alternately couple the intermediate terminal to the input terminal and the ground terminal.Type: GrantFiled: March 14, 2014Date of Patent: August 1, 2017Assignee: Volterra Semiconductor LLCInventors: Marco A. Zuniga, Chiteh Chiang, Yang Lu, Badredin Fatemizadeh, Amit Paul, Jun Ruan, Craig Cassella
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Patent number: 9159804Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.Type: GrantFiled: September 16, 2014Date of Patent: October 13, 2015Assignee: Volterra Semiconductor LLCInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Patent number: 8969158Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.Type: GrantFiled: January 28, 2014Date of Patent: March 3, 2015Assignee: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20140374826Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.Type: ApplicationFiled: September 16, 2014Publication date: December 25, 2014Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Patent number: 8866217Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.Type: GrantFiled: August 10, 2012Date of Patent: October 21, 2014Assignee: Volterra Semiconductor LLCInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20140266113Abstract: A voltage regulator has an input terminal and a ground terminal. The voltage regulator includes a high-side device, a low side device, and a controller. The high-side device is coupled between the input terminal and an intermediate terminal. The high-side device includes first and second transistors each coupled between the input terminal and the intermediate terminal, such that the first transistor controls a drain-source switching voltage of the second transistor. The low-side device is coupled between the intermediate terminal and the ground terminal. The controller drives the high-side and low-side devices to alternately couple the intermediate terminal to the input terminal and the ground terminal.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Chiteh Chiang, Yang Lu, Badredin Fatemizadeh, Amit Paul, Jun Ruan, Craig Cassella
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Publication number: 20140147979Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.Type: ApplicationFiled: January 28, 2014Publication date: May 29, 2014Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Patent number: 8709899Abstract: The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.Type: GrantFiled: August 10, 2012Date of Patent: April 29, 2014Assignee: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan, John Xia
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Patent number: 8647950Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.Type: GrantFiled: August 10, 2012Date of Patent: February 11, 2014Assignee: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20130115744Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.Type: ApplicationFiled: August 10, 2012Publication date: May 9, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20130105887Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.Type: ApplicationFiled: August 10, 2012Publication date: May 2, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Publication number: 20130109143Abstract: The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.Type: ApplicationFiled: August 10, 2012Publication date: May 2, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan, John Xia
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Publication number: 20130105888Abstract: The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.Type: ApplicationFiled: August 10, 2012Publication date: May 2, 2013Applicant: Volterra Semiconductor CorporationInventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
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Patent number: 7235827Abstract: A junction field effect transistor (JFET) has a gate region, drain region, and a source region. An epitaxial region having a first conductivity type is disposed over the drain region. The first conductivity type is N-type semiconductor material. The gate region is disposed within a trench which is formed in the epitaxial region. A P+ region is disposed within the epitaxial region and under the gate region. The P+ region has a first doping concentration of a second conductivity type opposite the first conductivity type. A P? region is disposed under the P+ region. The P? region has a second doping concentration of the second conductivity type which is less than the first doping concentration. The P? region may be disposed adjacent to a first portion of the P+ region while another P? region is disposed adjacent to a second portion of the P+ region. The P+ region may be implanted from the gate region deep into the epitaxial region.Type: GrantFiled: April 20, 2004Date of Patent: June 26, 2007Assignee: Power-One, Inc.Inventors: Badredin Fatemizadeh, Ali Salih
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Patent number: 7049677Abstract: A semiconductor device has a driver device (10) in proximity to a power device (12). In making the semiconductor device, an N+ layer (24) is formed on a substrate (22). A portion of the N+ layer is removed, substantially down to the substrate, to provide a layer offset (28) between the driver device area and power device area. An epi region of uniform thickness is formed over the driver device and power device areas. A portion of the epi layer is removed to provide another layer offset (70). An oxide layer (68) of uniform thickness is formed over the epi region. The oxide layer is planarized to remove oxide layer over the N+ layer. An oxide-filled trench (80) is formed between the driver device and the power device. The oxide-filled trench extends down to the oxide layer to isolate the driver device from the power device.Type: GrantFiled: January 28, 2004Date of Patent: May 23, 2006Assignee: Power-One, Inc.Inventors: Badredin Fatemizadeh, Ali Salih
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Publication number: 20050230745Abstract: A junction field effect transistor (JFET) has a gate region, drain region, and a source region. An epitaxial region having a first conductivity type is disposed over the drain region. The first conductivity type is N-type semiconductor material. The gate region is disposed within a trench which is formed in the epitaxial region. A P+ region is disposed within the epitaxial region and under the gate region. The P+ region has a first doping concentration of a second conductivity type opposite the first conductivity type. A P? region is disposed under the P+ region. The P? region has a second doping concentration of the second conductivity type which is less than the first doping concentration. The P? region may be disposed adjacent to a first portion of the P+ region while another P? region is disposed adjacent to a second portion of the P+ region. The P+ region may be implanted from the gate region deep into the epitaxial region.Type: ApplicationFiled: April 20, 2004Publication date: October 20, 2005Inventors: Badredin Fatemizadeh, Ali Salih
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Publication number: 20050161764Abstract: A semiconductor device has a driver device (10) in proximity to a power device (12). In making the semiconductor device, an N+ layer (24) is formed on a substrate (22). A portion of the N+ layer is removed, substantially down to the substrate, to provide a layer offset (28) between the driver device area and power device area. An epi region of uniform thickness is formed over the driver device and power device areas. A portion of the epi layer is removed to provide another layer offset (70). An oxide layer (68) of uniform thickness is formed over the epi region. The oxide layer is planarized to remove oxide layer over the N+ layer. An oxide-filled trench (80) is formed between the driver device and the power device. The oxide-filled trench extends down to the oxide layer to isolate the driver device from the power device.Type: ApplicationFiled: January 28, 2004Publication date: July 28, 2005Inventors: Badredin Fatemizadeh, Ali Salih