Abstract: The present disclosure relates to a three-dimensional (3D) package that has a die-on-die configuration, and includes a first die and at least one second die deposed underneath the first die. The first die includes a back-end-of-line (BEOL) portion, a device region over the BEOL portion, a substrate over the device region, and a substrate tie structure that extends through the device region and at least extends into the substrate. The substrate and the substrate tie structure each has a high thermal conductivity higher than 50 W/mK. The at least one second die is configured to be coupled to the BEOL portion of the first die, such that heat generated by the second die can propagate through the BEOL portion and the substrate tie structure, and radiate out of the first substrate.

Abstract: A broadband low noise amplifier (LNA) structure (10) includes a main LNA (12), an offset LNA (14), an input splitter (16), and an output combiner (18). The input splitter (16) is configured to split a radio frequency (RF) input signal into a first RF input signal and a second RF input signal with difference phases, which are fed to the main LNA (12) and the offset LNA (14), respectively. Based on the first RF input signal, the main LNA (12) is configured to provide a first RF output signal, and based on the second RF input signal, the offset LNA (14) is configured to provide a second RF output signal. The output combiner (18) is configured to realign the first RF output signal and the second RF output signal, and configured to combine the first and second RF output signals to provide a combined RF output signal.

Abstract: The present disclosure relates to a multi-level three-dimensional (3D) package with multiple package levels vertically stacked. Each package level includes a redistribution structure and a die section over the redistribution structure. Each die section includes a thinned die that includes substantially no silicon substrate and has a thickness between several micrometers and several tens of micrometers, a mold compound, and an intermediary mold compound. Herein, the thinned die and the mold compound are deposed over the redistribution structure, the mold compound surrounds the thinned die and extends vertically beyond a top surface of the thinned die to define an opening over the thinned die and within the mold compound, the intermediary mold compound resides over the thinned die and fills the opening within the inner mold compound, such that a top surface of the intermediary mold compound and a top surface of the mold compound are coplanar.

Abstract: The present disclosure pertains to a power amplifier system that promotes enhanced signal linearity and overall system efficiency. The system includes a power amplifier with an amplification path for a radio frequency (RF) signal, and detector circuitry operationally linked to sample locations along this path. The detector circuitry captures and transmits signal characteristics of the RF signal. A voltage standing wave ratio (VSWR) quadrant data generator in communication with the detector circuitry generates VSWR quadrant data based on the detected signal characteristics. The baseband circuitry, comprised of a memory unit preconfigured with digital pre-distortion (DPD) coefficients and a DPD processor, controls the shaping of pre-distortion applied to the RF signal based on the VSWR data, thereby enhancing signal linearity. The components of the system interconnect and collaboratively function to optimize the performance and efficiency of the power amplifier system.

Abstract: Systems and methods for analog predistortion (APD) in power amplifiers are disclosed. In one aspect, APD may be provided in a front-end module (FEM) of a transmitter. More specifically, the APD may include different predistortions based on where within a frequency band the signal to be distorted is operating (i.e., sub-band APD). The APD in the FEM may further be based on operating conditions such as temperature within the FEM. Still further, the FEM may be configured to apply different APD based on whether or not a baseband processor (BBP) applies digital predistortion (DPD). At a minimum, the provision of the APD may make the operation of a power amplifier in FEM more linear. Further, where DPD is present, the use of the APD may simplify the requirements for the DPD provided in the BBP.

Abstract: The present disclosure relates to an amplifier system having an output amplifier stage with a signal input and output, and a varactor with a capacitive output that is coupled to the signal input for adjusting input capacitance. The amplifier system also includes push varactor bias circuitry with a bias level output that is coupled to a tuning input, and a bias control input. The push varactor bias circuitry is configured to adjust bias voltage at the tuning input and thereby adjust the capacitance at the signal input by way of the varactor and reduce signal distortion at the signal output in response to a distortion compensation signal received at the bias control input.

Abstract: An analog predistortion system for power amplifiers is disclosed. In one aspect, the system may apply analog predistortion to offset memory effects that may occur as a function of frequencies that operate faster than time constants of the related circuits. In a particular aspect, the analog predistortion is applied at least to a phase of the signal to be amplified, but may also be applied to a gain of the signal to be amplified. When such memory focused analog predistortion is combined with memoryless or low depth memory digital predistortion, overall linearity and performance of the power amplifier is improved.

Abstract: Power protection loops for amplifier chain elements are disclosed. In one aspect, an amplifier chain may have a power detection circuit detect power within the amplifier chain. When the power exceeds a threshold, a control circuit limits amplification provided by amplifier element(s) within the amplifier chain to throttle or lower power levels within the amplifier chain, thereby protecting elements within the amplifier chain. In this fashion, not only may the amplifier element(s) be protected, but also acoustic filter elements may be protected. The threshold used to throttle or lower the power levels may be based on one or more of: a supply voltage, a sensed temperature, and a mode (e.g., 2G, 3G, 4G, 5G). By protecting these elements, these elements survive power surges instead of failing.

Abstract: A Doherty amplifier system is disclosed. The Doherty amplifier system includes a carrier amplifier having a carrier input and a carrier output, and a peaking amplifier having a peaking input coupled to the carrier input and a peaking output coupled to the carrier output. Analog pre-distortion circuitry is configured to linearize the carrier amplifier and linearize the peaking amplifier by compensating for base-to-collector capacitance loading of the carrier amplifier and the peaking amplifier during operation.

Abstract: The present disclosure describes a front-end module (FEM) and a process for making the same. In the disclosed FEM, a thinned flip-chip die, which includes a device region with a metal layer, resides over a module carrier. A mold compound resides over the module carrier, surrounds the thinned flip-chip die, and extends beyond a top surface of the thinned flip-chip die to define an opening over the top surface of the thinned flip-chip die and within the mold compound. A ferrimagnetic portion resides over the top surface of the thinned flip-chip die and within the opening, and a permanent magnetic portion resides over the ferrimagnetic portion and within the opening. Herein, the permanent magnetic portion, the ferrimagnetic portion, and the metal layer of the device region are vertically aligned, and form a circulator vertically stacked with the thinned flip-chip die.

Abstract: Low noise amplifiers (LNAs) are disclosed. In one aspect, an LNA may have distortion cancellation that is orthogonally implemented relative to noise cancellation such that changes to the distortion cancellation do not affect the noise cancellation. In further exemplary aspects, cancellation circuitry is added in parallel to a main or primary LNA path. The cancellation circuitry may include an initial impedance matching amplifier that effectuates noise cancellation and a second amplifier that effectuates distortion cancellation. Variations in the placement and composition of the second amplifier are provided. By providing a second path that allows for independent control of noise and distortion cancellation, overall performance of the LNA is improved.

Abstract: Disclosed is a low noise amplifier system. Included is a main amplifier having a main input coupled to a RF input and a main output connected to an RF output and an impedance amplifier having an impedance input coupled to the RF input and an impedance output coupled to the RF output, wherein the impedance amplifier is configured to provide input impedance matching to the main amplifier. The impedance amplifier also provides a first noise path that passes through the impedance amplifier such that the noise generated by the impedance amplifier is substantially out of phase with the noise that passes through a second noise path that passes through the main amplifier.

Abstract: Disclosed is a low noise amplifier system. Included is a main amplifier having a main input coupled to a RF input and a main output connected to an RF output and an impedance amplifier having an impedance input coupled to the RF input and an impedance output coupled to the RF output, wherein the impedance amplifier is configured to provide input impedance matching to the main amplifier. The impedance amplifier also provides a first noise path that passes through the impedance amplifier such that the noise generated by the impedance amplifier is substantially out of phase with the noise that passes through a second noise path that passes through the main amplifier. A neutralization amplifier is configured to reduce parasitic capacitive loading within the first noise path.

Abstract: Amplitude modulation-phase modulation (AM-PM) linearization in power amplifier techniques are disclosed. In one aspect, a fixed capacitor is placed in parallel to a cascode device within a power amplifier. The sum of capacitances from the cascode device and the parallel capacitor may be relatively fixed across voltage swings, allowing for small phase changes across a wide range of signal amplitudes passing through the power amplifier. The small phase changes across voltage swings make it easier to provide compensation for such phase changes resulting in a more efficient device.

Abstract: Amplitude modulation-phase modulation (AM-PM) linearization in a power amplifier using bias circuitry, which fixes a bias of a cascode transistor within a power amplifier is disclosed. In particular, the cascode transistor may switch between operation in a saturation mode and a triode mode. The bias is set such that the cascode transistor operates at a fixed duty cycle in the triode mode relative to the saturation mode for a wide range of signal levels from small-signal to large-signal. An exemplary duty cycle is fifty percent (50%), although other duty cycles may be used. This bias will result in a constant capacitance contributed by the cascode device to the power amplifier over a wide signal level range.

Abstract: Disclosed is a power amplifier system having a main amplifier with an input coupled to a main radio frequency (RF) input and an output connected to a main RF output, wherein the main amplifier exhibits a nonlinear gain characteristic with compression. At least one compression compensating amplifier has a signal input coupled to the common RF input and a signal output coupled to the common RF output.

Abstract: A power amplifier with clamp and feedback protection circuitry is disclosed. In one aspect, the power amplifier is initially protected by a fast-acting clamp circuit whose overall size is relatively limited. Subsequent operation allows a comparatively slowly acting feedback loop to dominate the protection of the power amplifier. By providing the two protection circuits, each optimized for a particular phase of protection, the overall size of associated protection circuitry may be diminished while still protecting the power amplifier from failure inducing conditions.

Abstract: A power amplifier system is disclosed having a first amplifier with a high-power input and a high-power output. A second amplifier has a low-power input and a low-power output. A reconfigurable mode switch network has a first series switch branch coupled between the high-power output and an RF output, a first shunt branch is coupled between the RF output and a fixed voltage node, and a second series switch branch is coupled between the low-power output and a shared node of the first shunt branch. The shared node separates the first shunt branch into a first shared section that is between the RF output and the shared node and a second shared section that is between the shared node and the fixed voltage node.

Abstract: A power amplifier with feedback ballast resistance is disclosed. In one aspect, a power amplifier cell may receive a bias signal from a bias circuit where the bias circuit includes a feedback loop having an impedance that, from the perspective of the bias signal is relatively low impedance, but from a ballast thermal control perspective provides sufficient resistance to avoid thermal runaway. In exemplary aspects, this feedback loop may be extended to operate with multiple power amplifier cells and provide differential mode thermal control optimized for individual cell bias signal control and common mode thermal control optimized for thermal control of the collective power amplifier cells of the power amplifier.

Abstract: A power amplifier using multi-path common-mode feedback loops for radio frequency linearization is disclosed. In one aspect, a complementary metal oxide semiconductor (CMOS) power amplifier containing cascoded n-type field effect transistors (NFETs) and cascoded p-type FETs (PFETs) may have a common-mode feedback network and provides bias voltages that are dynamically varying with the signal power to keep the output common-mode fixed around a half-supply level, while the small-signal and large-signal transconductances of the FET's are kept balanced. A further feedback network may be associated with the supply voltage to assist in providing a symmetrical supply signal. The symmetrical supply signal allows for supply variations without introducing distortion for the power amplifier stage.