Abstract: Systems and methods are disclosed to perform a function level reset in a memory controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a storage controller circuit configured to receive a function reset indicator from a host device, the function reset indicator identifying a selected storage controller function executing at a storage controller of the apparatus. The circuit may abort each command associated with the selected function and pending at the apparatus based on the function reset indicator, verify that no commands associated with the selected function remain pending at the apparatus, and clear registers associated with the selected function based on the determination that no commands associated with the selected function remain.

Abstract: Systems and methods are disclosed to abort a command at a data storage controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a data storage controller configured to receive an abort indicator from a host device, generate an abort tracking indicator at a receiving unit configured to receive commands from the host device, monitor to determine when the selected command is received at the receiving unit based on the abort tracking indicator, and abort the selected command when the selected command is received at the receiving unit. In some embodiments, the data storage controller may generate an abort tracking indicator at a completion unit configured to notify the host device of completed commands, and monitor for the selected command at the completion unit based on the abort tracking indicator.

Abstract: Systems and methods are disclosed to perform a function level reset in a memory controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a storage controller circuit configured to receive a function reset indicator from a host device, the function reset indicator identifying a selected storage controller function executing at a storage controller of the apparatus. The circuit may abort each command associated with the selected function and pending at the apparatus based on the function reset indicator, verify that no commands associated with the selected function remain pending at the apparatus, and clear registers associated with the selected function based on the determination that no commands associated with the selected function remain.

Abstract: Method and apparatus for managing data in a distributed data storage system. In some embodiments, a plurality of storage devices define an overall available memory space. A control circuit stores a first copy of user data from a selected distributed data set in a working set of memory buffers, stores a duplicate, second copy of the user data in an alias set of memory buffers, generates parity data based on the second copy of the user data in the alias set of the memory buffers, and flushes the user data and the parity data from the alias set of memory buffers to the storage devices while the first copy of the user data remains in the working set of the memory buffers. In this way, subsequently received access commands can be serviced using the working set of the memory buffers.

Abstract: The disclosed technology provides for selection of a subset of available non-volatile memory devices in an array to receive a dirty cache data of a volatile cache responsive to detection of a power failure. In one implementation, the selection of the non-volatile memory devices is based on one or more predictive power parameters usable to estimate a time remaining during which a reserve power supply can support a cache offload to the selected subset of devices.

Abstract: Systems and methods are disclosed to delete a command queue, in accordance with certain embodiments of the present disclosure. An apparatus may comprise a circuit configured to receive a queue deletion indicator from a host device, including a queue identifier for a selected command queue to be deleted. The circuit may abort each command associated with the selected command queue and pending at the apparatus based on the queue identifier. Commands associated with the selected queue may be identified in a command table and flagged with an abort bit, which may signal an I/O processing pipeline to abort the command when encountered. The circuit may verify that no commands associated with the selected command queue remain pending at the apparatus, and send a completion indicator to notify the host device that the selected command queue is deleted.

Abstract: In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache locations without regard to whether any read requests to the corresponding logical addresses are pending. After the data has been written, and again without regard to whether any read requests are pending against the corresponding logical addresses, metadata is updated to associate the cache locations with the logical addresses. A count of data access requests pending against each cache location having valid data is maintained, and a cache location is only returned to the free list when the count indicates no data access requests are pending against the cache location.

Abstract: The disclosed technology provides for off-loading dirty data from a volatile cache memory to multiple non-volatile memory devices responsive to detection of a power failure. The arrangement of the dirty data is describable by a cache image, which is reconstructed within the volatile memory from the non-volatile memory devices responsive to detection of power restoration following the power failure.

Abstract: Systems and methods are disclosed to abort a command at a data storage controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a data storage controller configured to receive an abort indicator from a host device, generate an abort tracking indicator at a receiving unit configured to receive commands from the host device, monitor to determine when the selected command is received at the receiving unit based on the abort tracking indicator, and abort the selected command when the selected command is received at the receiving unit. In some embodiments, the data storage controller may generate an abort tracking indicator at a completion unit configured to notify the host device of completed commands, and monitor for the selected command at the completion unit based on the abort tracking indicator.

Abstract: The disclosed technology provides for selection of a subset of available non-volatile memory devices in an array to receive a dirty cache data of a volatile cache responsive to detection of a power failure. In one implementation, the selection of the non-volatile memory devices is based on one or more predictive power parameters usable to estimate a time remaining during which a reserve power supply can support a cache offload to the selected subset of devices.

Abstract: The disclosed technology provides for off-loading dirty data from a volatile cache memory to multiple non-volatile memory devices responsive to detection of a power failure. The arrangement of the dirty data is describable by a cache image, which is reconstructed within the volatile memory from the non-volatile memory devices responsive to detection of power restoration following the power failure.

Abstract: Method and apparatus for managing data in a distributed data storage system. In some embodiments, a plurality of storage devices define an overall available memory space. A control circuit stores a first copy of user data from a selected distributed data set in a working set of memory buffers, stores a duplicate, second copy of the user data in an alias set of memory buffers, generates parity data based on the second copy of the user data in the alias set of the memory buffers, and flushes the user data and the parity data from the alias set of memory buffers to the storage devices while the first copy of the user data remains in the working set of the memory buffers. In this way, subsequently received access commands can be serviced using the working set of the memory buffers.

Abstract: In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache locations without regard to whether any read requests to the corresponding logical addresses are pending. After the data has been written, and again without regard to whether any read requests are pending against the corresponding logical addresses, metadata is updated to associate the cache locations with the logical addresses. A count of data access requests pending against each cache location having valid data is maintained, and a cache location is only returned to the free list when the count indicates no data access requests are pending against the cache location.

Abstract: Described embodiments provide for dynamically controlling a scheduling rate of each node in a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. A traffic manager enqueues received tasks in a queue of the scheduling hierarchy associated with a data flow. The queue has a parent scheduler at each level of the hierarchy up to the root scheduler. The traffic manager maintains one or more scheduling data structures for each node in the scheduling hierarchy. If the traffic manager receives a rate reduction request corresponding to a given node of the scheduling hierarchy, the traffic manager updates one or more indicators in the scheduling data structure corresponding to the given node and removes the given node from the scheduling hierarchy, thereby reducing the scheduling rate of the node.

Abstract: Described embodiments provide a method of processing packets of a network processor. One or more tasks are generated corresponding to received packets associated with one or more data flows. A traffic manager receives a task corresponding to a data flow, the task provided by a processing module of the network processor. The traffic manager determines whether the received task corresponds to a unicast data flow or a multicast data flow. If the received task corresponds to a multicast data flow, the traffic manager determines, based on identifiers corresponding to the task, an address of launch data stored in launch data tables in a shared memory, and reads the launch data. Based on the identifiers and the read launch data, two or more output tasks are generated corresponding to the multicast data flow, and the two or more output tasks are added at the tail end of a scheduling queue.

Abstract: Described embodiments provide for queuing tasks in a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager performs a task enqueue operation for the task. The task enqueue operation includes adding the received task to an associated queue of the scheduling hierarchy, where the queue is associated with a data flow of the received task. The queue has a corresponding scheduler level M, where M is a positive integer less than or equal to N. Starting at the queue and iteratively repeating at each scheduling level until reaching the root scheduler, each node in the scheduling hierarchy maintains an actual count of tasks corresponding to the node. Each node communicates a capped task count to a corresponding parent scheduler at a relative next scheduler level.

Abstract: Described embodiments provide for scheduling packets for transmission by a network processor. The network processor generates tasks corresponding to received packets associated with a data flow. A traffic manager of the network processor receives tasks provided by a processing module of the network processor and generates a tree scheduling hierarchy having one or more scheduling levels. Each received task is queued in a queue of the scheduling hierarchy associated with the received task, the queue having a corresponding parent scheduler in each level of the scheduling hierarchy, forming a branch of the scheduling hierarchy. A parent scheduler selects a child node to transmit a task. A task read module determines a thread corresponding to the selected child node to read corresponding packet data from a shared memory. The traffic manager forms one or more output tasks for transmission based on the packet data corresponding to the thread.

Abstract: Described embodiments provide for controlling a state of each node in a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. A traffic manager enqueues received tasks in a queue of the scheduling hierarchy associated with a data flow. The traffic manager maintains scheduling data structures for each node in the scheduling hierarchy. The scheduling data structures include a backpressure indicator and a timer indicator. If the backpressure indicator is set, the traffic manager sets the node as unavailable for scheduling and removes the node from the scheduling hierarchy. If the timer indicator is set, the traffic managers sets the node as unavailable for scheduling. Otherwise, if neither the backpressure indicator nor the timer indicator is set, the traffic manager sets the node as available for scheduling.

Abstract: Described embodiments provide for dynamically constructing a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager queues the received task in the associated queue, the queue having a corresponding parent scheduler at each of one or more next levels of the scheduling hierarchy up to the root scheduler. A parent scheduler selects, starting at the root scheduler and iteratively repeating at each of the corresponding N scheduling levels until a queue is selected, a child node to transmit at least one task. The traffic manager forms output packets for transmission based on the at least one task from the selected queue.

Abstract: Described embodiments provide sharing data between nodes in a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets, each task having a shared parameter ID. The traffic manager determines the shared parameter ID value of the received task and queues the received task in a queue of the scheduling hierarchy. The queue has a scheduler level M and a parent scheduler at each of M?1 levels in the scheduling hierarchy. The traffic manager determines a shared parameter ID value of the queue. The traffic manager loads, from a shared memory to a corresponding level one cache, one or more shared parameter values corresponding to at least one of the determined shared parameter ID value of the received task and the determined shared parameter ID value of the queue.