Patents by Inventor Balasubramanian S. Pranatharthi Haran
Balasubramanian S. Pranatharthi Haran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180114834Abstract: A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.Type: ApplicationFiled: October 24, 2016Publication date: April 26, 2018Inventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John Zhang
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Patent number: 9741609Abstract: A method of fabricating features of a semiconductor device includes forming a contact over a substrate, the contact including a cobalt core and a liner layer arranged on sidewalls, wherein the contact includes a portion that is laterally surrounded by an interlevel dielectric (ILD); depositing another layer of ILD on the contact; etching a first opening in the ILD to expose a surface of the contact; removing the liner layer of the contact to expose a portion of the cobalt core; etching the ILD that laterally surrounds the contact to form a second opening beneath the first opening, the second opening having a width that is less than the first opening; depositing a liner on sidewalls of the first opening, the second opening, and directly on the cobalt core; and depositing a metal on the liner layer to form an interconnect structure.Type: GrantFiled: November 1, 2016Date of Patent: August 22, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John H. Zhang
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Patent number: 9704991Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having self-aligned spacer protection layers. The method includes forming a first sacrificial gate adjacent to a second sacrificial gate on a substrate. A dielectric layer is formed on the substrate and above top surfaces of the first and second sacrificial gates. A self-aligned protection region is formed to cover a first portion of the dielectric layer and a second uncovered portion of the dielectric layer is removed. The first portion of the dielectric layer defines a spacer after the second portion of the dielectric layer is removed.Type: GrantFiled: October 31, 2016Date of Patent: July 11, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John Zhang
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Patent number: 9455254Abstract: One method disclosed herein includes, among other things, forming a gate cap layer above a recessed final gate structure and above recessed sidewall spacers, forming a recessed trench silicide region that is conductively coupled to the first source/drain region, the recessed trench silicide region having an upper surface that is positioned at a level that is below the recessed upper surface of the sidewall spacers, forming a combined contact opening in at least one layer of material that exposes a conductive portion of the recessed final gate structure and a portion of the trench silicide region, and forming a combined gate and source/drain contact structure in the combined contact opening.Type: GrantFiled: November 7, 2014Date of Patent: September 27, 2016Assignees: GLOBALFOUNDRIES Inc., International Business Machines CorporationInventors: Ruilong Xie, Andre Labonte, Su Chen Fan, Balasubramanian S. Pranatharthi Haran
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Publication number: 20160133623Abstract: One method disclosed herein includes, among other things, forming a gate cap layer above a recessed final gate structure and above recessed sidewall spacers, forming a recessed trench silicide region that is conductively coupled to the first source/drain region, the recessed trench silicide region having an upper surface that is positioned at a level that is below the recessed upper surface of the sidewall spacers, forming a combined contact opening in at least one layer of material that exposes a conductive portion of the recessed final gate structure and a portion of the trench silicide region, and forming a combined gate and source/drain contact structure in the combined contact opening.Type: ApplicationFiled: November 7, 2014Publication date: May 12, 2016Inventors: Ruilong Xie, Andre Labonte, Su Chen Fan, Balasubramanian S. Pranatharthi Haran
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Patent number: 9331174Abstract: A semiconductor substrate including a field effect transistor (FET) and a method of producing the same wherein a stressor is provided in a recess before the source/drain region is formed. The device has an increased carrier mobility in the channel region adjacent to the gate electrode.Type: GrantFiled: April 15, 2010Date of Patent: May 3, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Bruce B. Doris, Johnathan E. Faltermeier, Lahir M. Shaik Adam, Balasubramanian S. Pranatharthi Haran
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Patent number: 8334090Abstract: An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.Type: GrantFiled: January 28, 2011Date of Patent: December 18, 2012Assignee: International Business Machines CorporationInventors: Nicholas C. Fuller, Michael A. Guillorn, Balasubramanian S. Pranatharthi Haran, Jyotica V. Patel
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Patent number: 8101518Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A. selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.Type: GrantFiled: June 11, 2008Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Michael A. Cobb, Asa Frye, Balasubramanian S. Pranatharthi Haran, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Andrew P. Mansson, Renee T. Mo, Jay W. Strane, Horatio S. Wildman
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Publication number: 20110254015Abstract: A semiconductor substrate including a field effect transistor (FET) and a method of producing the same wherein a stressor is provided in a recess before the source/drain region is formed. The device has an increased carrier mobility in the channel region adjacent to the gate electrode.Type: ApplicationFiled: April 15, 2010Publication date: October 20, 2011Applicant: International Business Machines CorporationInventors: Bruce B. Doris, Johnathan E. Faltermeier, Lahir M. Shaik Adam, Balasubramanian S. Pranatharthi Haran
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Publication number: 20110123779Abstract: An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.Type: ApplicationFiled: January 28, 2011Publication date: May 26, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicholas C. Fuller, Michael A. Guillorn, Balasubramanian S. Pranatharthi Haran, Jyotica V. Patel
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Patent number: 7914970Abstract: An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.Type: GrantFiled: October 4, 2007Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: Nicholas C. Fuller, Michael A. Guillorn, Balasubramanian S. Pranatharthi Haran, Jyotica V. Patel
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Patent number: 7544610Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.Type: GrantFiled: September 7, 2004Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Michael A. Cobb, Asa Frye, Balasubramanian S. Pranatharthi Haran, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Andrew P. Mansson, Renee T. Mo, Jay W. Strane, Horatio S. Wildman
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Publication number: 20090092799Abstract: An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.Type: ApplicationFiled: October 4, 2007Publication date: April 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicholas C. Fuller, Michael A. Guillorn, Balasubramanian S. Pranatharthi Haran, Jyotica V. Patel
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Patent number: 7501345Abstract: Silicide formation processes are disclosed that use an electrochemical displacement reaction in the absence of an externally applied current or potential. In an embodiment, a method for forming an integrated circuit comprises: depositing a metallic material upon select areas of a semiconductor topography comprising silicon by contacting the semiconductor topography with an aqueous solution comprising an acid and a metal salt to cause an electrochemical displacement reaction in the absence of an externally applied current or potential, wherein a concentration of the metal salt in the aqueous solution is about 0.01 millimolar to about 0.5 millimolar; and annealing the metallic material to form a silicide upon the areas of the semiconductor topography comprising the silicon.Type: GrantFiled: March 28, 2008Date of Patent: March 10, 2009Assignee: International Business Machines CorporationInventors: Veeraraghaven S. Basker, Hariklia Deligianni, Balasubramanian S. Pranatharthi Haran, James J. Kelly, Christian Lavoie, George G. Totir
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Publication number: 20080274611Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.Type: ApplicationFiled: June 11, 2008Publication date: November 6, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Michael A. Cobb, Asa Frye, Balasubramanian S. Pranatharthi Haran, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Andrew P. Mansson, Renee T. Mo, Jay W. Strane, Horatio S. Wildman