Patents by Inventor Balint Fleischer
Balint Fleischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240160585Abstract: A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.Type: ApplicationFiled: January 22, 2024Publication date: May 16, 2024Applicant: Intel CorporationInventors: Debendra Das Sharma, Robert G. Blankenship, Suresh S. Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen, Mohan J. Kumar, Brian S. Morris
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Patent number: 11886358Abstract: An apparatus includes a memory component having a plurality of ball grid array (BGA) components, wherein each respective one of the BGA components includes a plurality of memory blocks and a BGA component controller and firmware adjacent the plurality of memory blocks to manage the plurality of memory blocks. The apparatus further includes a processing device, included in the memory component, to perform memory operations on the BGA components.Type: GrantFiled: April 11, 2022Date of Patent: January 30, 2024Assignee: Micron Technology, Inc.Inventors: Suresh Rajgopal, Balint Fleischer
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Publication number: 20220237131Abstract: An apparatus includes a memory component having a plurality of ball grid array (BGA) components, wherein each respective one of the BGA components includes a plurality of memory blocks and a BGA component controller and firmware adjacent the plurality of memory blocks to manage the plurality of memory blocks. The apparatus further includes a processing device, included in the memory component, to perform memory operations on the BGA components.Type: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Inventors: Suresh Rajgopal, Balint Fleischer
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Patent number: 11301401Abstract: An apparatus includes a memory component having a plurality of ball grid array (BGA) components, wherein each respective one of the BGA components includes a plurality of memory blocks and a BGA component controller and firmware adjacent the plurality of memory blocks to manage the plurality of memory blocks. The apparatus further includes a processing device, included in the memory component, to perform memory operations on the BGA components.Type: GrantFiled: December 18, 2020Date of Patent: April 12, 2022Assignee: Micron Technology, Inc.Inventors: Suresh Rajgopal, Balint Fleischer
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Publication number: 20220012189Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.Type: ApplicationFiled: September 25, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: Debendra Das Sharma, Robert G. Blankenship, Suresh S. Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen, Mohan J. Kumar, Brian S. Morris
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Publication number: 20210303482Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.Type: ApplicationFiled: February 8, 2021Publication date: September 30, 2021Applicant: Intel CorporationInventors: Debendra Das Sharma, Robert G. Blankenship, Suresh S. Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen, Mohan J. Kumar, Brian S. Morris
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Patent number: 11086520Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.Type: GrantFiled: July 12, 2019Date of Patent: August 10, 2021Assignee: Intel CorporationInventors: Mark A. Schmisseur, Mohan J. Kumar, Balint Fleischer, Debendra Das Sharma, Raj K. Ramanujan
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Patent number: 10915468Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.Type: GrantFiled: December 26, 2013Date of Patent: February 9, 2021Assignee: Intel CorporationInventors: Debendra Das Sharma, Robert G. Blankenship, Suresh S. Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen, Mohan J. Kumar, Brian S. Morris
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Publication number: 20200004429Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.Type: ApplicationFiled: July 12, 2019Publication date: January 2, 2020Inventors: Mark A. SCHMISSEUR, Mohan J. KUMAR, Balint FLEISCHER, Debendra DAS SHARMA, Raj K. RAMANUJAN
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Patent number: 10359940Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.Type: GrantFiled: November 7, 2017Date of Patent: July 23, 2019Assignee: Intel CorporationInventors: Mark A. Schmisseur, Mohan J. Kumar, Balint Fleischer, Debendra Das Sharma, Raj Ramanujan
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Patent number: 10296399Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.Type: GrantFiled: June 9, 2016Date of Patent: May 21, 2019Assignee: Intel CorporationInventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
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Patent number: 10229024Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.Type: GrantFiled: June 8, 2016Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
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Publication number: 20180157424Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.Type: ApplicationFiled: November 7, 2017Publication date: June 7, 2018Inventors: Mark A. SCHMISSEUR, Mohan J. KUMAR, Balint FLEISCHER, Debendra DAS SHARMA, Raj Ramanujan
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Patent number: 9977618Abstract: An apparatus for pooling memory resources across multiple nodes is described herein. The apparatus includes a shared memory controller, wherein each node of the multiple nodes is connected to the shared memory controller. The apparatus also includes a pool of memory connected to the shared memory controller, wherein a portion of the pool of memory is allocated to each node of the multiple nodes.Type: GrantFiled: December 27, 2013Date of Patent: May 22, 2018Assignee: Intel CorporationInventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
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Patent number: 9823849Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.Type: GrantFiled: June 26, 2015Date of Patent: November 21, 2017Assignee: INTEL CORPORATIONInventors: Mark A. Schmisseur, Mohan J. Kumar, Balint Fleischer, Debendra Das Sharma, Raj K. Ramanujan
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Publication number: 20170052860Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.Type: ApplicationFiled: June 8, 2016Publication date: February 23, 2017Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
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Publication number: 20170046208Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.Type: ApplicationFiled: June 9, 2016Publication date: February 16, 2017Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
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Publication number: 20170004098Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.Type: ApplicationFiled: December 26, 2013Publication date: January 5, 2017Applicant: Intel CorporationInventors: Debendra Das Sharma, Robert G. Blankenship, Suresh S. Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen, Mohan J. Kumar, Brian S. Morris
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Publication number: 20160378353Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.Type: ApplicationFiled: June 26, 2015Publication date: December 29, 2016Inventors: Mark A. SCHMISSEUR, Mohan J. KUMAR, Balint FLEISCHER, Debendra DAS SHARMA, Raj K. Ramanujan
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Patent number: 9372752Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.Type: GrantFiled: December 27, 2013Date of Patent: June 21, 2016Assignee: Intel CorporationInventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer