Patents by Inventor Balkrishna R. Rashingkar
Balkrishna R. Rashingkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10896280Abstract: Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.Type: GrantFiled: June 17, 2019Date of Patent: January 19, 2021Assignee: Synopsys, Inc.Inventors: Balkrishna R. Rashingkar, Leonardos J. van Bokhoven, Peiqing Zou
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Patent number: 10372860Abstract: Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.Type: GrantFiled: July 1, 2015Date of Patent: August 6, 2019Assignee: SYNOPSYS, INC.Inventors: Balkrishna R. Rashingkar, Leonardus J. van Bokhoven, Peiqing Zou
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Patent number: 10318692Abstract: Some embodiments can receive a netlist for the circuit design, wherein the netlist is divided into a set of blocks and a top-level netlist. Next, the embodiments can create (1) a top-level netlist abstraction based on the top-level netlist, and (2) for each block in the set of blocks, create a block abstraction based on a portion of the netlist that is in the block and create virtual pin cells in the block, wherein each virtual pin cell corresponds to a connection that crosses a boundary of the block. The embodiments can then place the top-level netlist abstraction in the layout area, the set of blocks in the layout area, the block abstractions in corresponding blocks, and the virtual pin cells in corresponding blocks. The placed circuit abstraction can then be used to drive standard cell placement in the circuit design.Type: GrantFiled: March 23, 2015Date of Patent: June 11, 2019Assignee: SYNOPSYS, INC.Inventors: Douglas Chang, Balkrishna R. Rashingkar
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Patent number: 9747403Abstract: A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG constraints for each block in the set of blocks. The new sets of PG constraints can then be provided to one or more instances of a PG compiler that executes on one or more processors to create the PG network for the chip layout.Type: GrantFiled: July 13, 2015Date of Patent: August 29, 2017Assignee: SYNOPSYS, INC.Inventors: Yi-Min Jiang, Xiang Qui, Balkrishna R. Rashingkar, Yan Lin
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Publication number: 20170017746Abstract: A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG constraints for each block in the set of blocks. The new sets of PG constraints can then be provided to one or more instances of a PG compiler that executes on one or more processors to create the PG network for the chip layout.Type: ApplicationFiled: July 13, 2015Publication date: January 19, 2017Applicant: SYNOPSYS, INC.Inventors: Yi-Min Jiang, Xiang Qui, Balkrishna R. Rashingkar, Yan Lin
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Publication number: 20170004240Abstract: Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.Type: ApplicationFiled: July 1, 2015Publication date: January 5, 2017Applicant: SYNOPSYS, INC.Inventors: Balkrishna R. Rashingkar, Leonardus J. van Bokhoven, Peiqing Zou
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Patent number: 9460258Abstract: Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping.Type: GrantFiled: December 26, 2013Date of Patent: October 4, 2016Assignee: SYNOPSYS, INC.Inventors: David L. Peart, Yan Lin, Aiguo Lu, Balkrishna R. Rashingkar, Russell B. Segal, Peiqing Zou
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Publication number: 20160283632Abstract: Some embodiments can receive a netlist for the circuit design, wherein the netlist is divided into a set of blocks and a top-level netlist. Next, the embodiments can create (1) a top-level netlist abstraction based on the top-level netlist, and (2) for each block in the set of blocks, create a block abstraction based on a portion of the netlist that is in the block and create virtual pin cells in the block, wherein each virtual pin cell corresponds to a connection that crosses a boundary of the block. The embodiments can then place the top-level netlist abstraction in the layout area, the set of blocks in the layout area, the block abstractions in corresponding blocks, and the virtual pin cells in corresponding blocks. The placed circuit abstraction can then be used to drive standard cell placement in the circuit design.Type: ApplicationFiled: March 23, 2015Publication date: September 29, 2016Applicant: SYNOPSYS, INC.Inventors: Douglas Chang, Balkrishna R. Rashingkar
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Patent number: 9026974Abstract: Methods and apparatuses are described for facilitating a user to explore and evaluate different options during floorplanning. Some embodiments display a graphical representation of a circuit design floorplan, wherein the graphical representation includes a set of blocks and a set of flylines between blocks, wherein each block corresponds to a portion of the circuit design, and wherein each flyline corresponds to one or more relationships between two blocks. Additionally, a set of metrics associated with one or more blocks or one or more flylines can be displayed. Next, in response to receiving a modification to one or more blocks in the graphical representation, the embodiments can update the set of metrics without performing expensive netlist modification, placement, routing, and/or propagation of timing information through multiple levels of logic, and then display the updated set of metrics.Type: GrantFiled: December 24, 2013Date of Patent: May 5, 2015Assignee: Synopsys, Inc.Inventors: Russell B. Segal, Balkrishna R. Rashingkar, Douglas Chang, Mattias A. Hembruch
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Patent number: 8910097Abstract: Systems and techniques for creating a netlist abstraction are described. During operation, an embodiment can receive a netlist for a circuit design, wherein circuit elements in the circuit design are organized in a logical hierarchy (LH). Next, the embodiment can receive a set of LH nodes in the LH. The embodiment can then create the netlist abstraction by, for each LH node in the set of LH nodes, replacing a portion of the netlist that is below the LH node by a star netlist, wherein the star netlist includes a center object that is electrically connected to a set of satellite objects, wherein each satellite object corresponds to a port of the LH node.Type: GrantFiled: March 22, 2013Date of Patent: December 9, 2014Assignee: Synopsys, Inc.Inventors: Douglas Chang, Balkrishna R. Rashingkar
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Patent number: 8893073Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.Type: GrantFiled: December 27, 2012Date of Patent: November 18, 2014Assignee: Synopsys, Inc.Inventors: Balkrishna R. Rashingkar, David L. Peart, Russell Segal, Douglas Chang, Ksenia Roze
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Publication number: 20140189617Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Applicant: SYNOPSYS, INC.Inventors: Balkrishna R. Rashingkar, David L. Peart, Russell Segal, Douglas Chang, Ksenia Roze
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Publication number: 20140189620Abstract: Systems and techniques for creating a netlist abstraction are described. During operation, an embodiment can receive a netlist for a circuit design, wherein circuit elements in the circuit design are organized in a logical hierarchy (LH). Next, the embodiment can receive a set of LH nodes in the LH. The embodiment can then create the netlist abstraction by, for each LH node in the set of LH nodes, replacing a portion of the netlist that is below the LH node by a star netlist, wherein the star netlist includes a center object that is electrically connected to a set of satellite objects, wherein each satellite object corresponds to a port of the LH node.Type: ApplicationFiled: March 22, 2013Publication date: July 3, 2014Applicant: Synopsys, Inc.Inventors: Douglas Chang, Balkrishna R. Rashingkar
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Publication number: 20140181776Abstract: Methods and apparatuses are described for facilitating a user to explore and evaluate different options during floorplanning. Some embodiments display a graphical representation of a circuit design floorplan, wherein the graphical representation includes a set of blocks and a set of flylines between blocks, wherein each block corresponds to a portion of the circuit design, and wherein each flyline corresponds to one or more relationships between two blocks. Additionally, a set of metrics associated with one or more blocks or one or more flylines can be displayed. Next, in response to receiving a modification to one or more blocks in the graphical representation, the embodiments can update the set of metrics without performing expensive netlist modification, placement, routing, and/or propagation of timing information through multiple levels of logic, and then display the updated set of metrics.Type: ApplicationFiled: December 24, 2013Publication date: June 26, 2014Applicant: Synopsys, Inc.Inventors: Russell B. Segal, Balkrishna R. Rashingkar, Douglas Chang, Mattias A. Hembruch
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Publication number: 20140181773Abstract: Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping.Type: ApplicationFiled: December 26, 2013Publication date: June 26, 2014Applicant: Synopsys, Inc.Inventors: David L. Peart, Yan Lin, Aiguo Lu, Balkrishna R. Rashingkar, Russell B. Segal, Peiqing Zou