Abstract: A semiconductor read/write memory device has a normal mode of operation and a test mode. The test mode allows concurrent writing to a number of cells in the cell array so that test patterns may be rapidly loaded. The cell array is split into subarrays and the column addressing circuitry is arranged to provide a maximum of spacing between the cells that are concurrently written. In this manner, pattern sensitivity tests may be run at higher speed because a number of bits at widely spaced positions in the array can be tested simultaneously.

Abstract: A register of the type used on as address counter in a dynamic RAM is tested by a method which does not require cycling through every possible value of the register contents. The counter is first loaded with a fixed value, all 1's or all 0's, and the contents checked by an AND or OR gate, producing a one-bit output which is monitored off-chip. Then, the carry feedback path to the counter register is altered, as by inverting all but the LSB, and the contents again checked, using the one-bit output via the AND or OR. In this manner, the operation of the counter is tested in three cycles.

Abstract: A register of the type used on as address counter in a dynamic RAM is tested by a method which does not require cycling through every possible value of the register contents. The counter is first loaded with a fixed value, all 1's or all 0's, and the contents checked by an AND or OR gate, producing a one-bit output which is monitored off-chip. Then, the carry feedback path to the counter register is altered, as by inverting all but the LSB, and the contents again checked, using the one-bit output via the AND or OR. In this manner, the operation of the counter is tested in three cycles.

Abstract: A semiconductor read/write memory device of the type using dynamic one-transistor storage cells employs dummy capacitors which are the same size as the storage capacitors, and these dummy capacitors are precharged to a reference voltage level less than half the supply voltage. A voltage divider sets the precharge level, but this divider is shunted by a control device initially so the dummy capacitors are quickly discharged to the reference level. A comparator with differential inputs determines when the reference level has reached the proper value, then the control device and the comparator are shut off to reduce power, and the reference level maintained by the voltage divider. The dummy capacitor precharge starts during the later part of an active cycle, so the specified cycle time can be minimized.

Abstract: A semiconductor read/write memory device has a normal mode of operation and a test mode. The test mode allows concurrent writing to a number of cells in the cell array so that test patterns may be rapidly loaded. The cell array is split into subarrays and the column addressing circuitry is arranged to provide a maximum of spacing between the cells that are concurrently written. In this manner, pattern sensitivity tests may be run at higher speed because a number of bits at widely spaced positions in the array can be tested simultaneously.

Abstract: A semiconductor dynamic read/write memory device has serial data input/output modes, such as the so-called nibble, byte or extended nibble modes. This device employs improved address counter circuitry to access data from a selected row. An initial column address is latched when a serial mode is initiated, and the counter steps through the programmed number of bits, starting at the initial address. The number of bits used in the serial mode may be selected by metal-mask programming. To avoid a speed penalty, look-ahead circuitry initiates the set up for serial mode before the controls for this mode are detected.