Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

Abstract: Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.

Abstract: Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

Abstract: Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.

Abstract: A system and computer implemented method of modifying characteristics of a circuit provide enhanced performance. One embodiment of the method provides for determining a set of objective parameters for the circuit and receiving noise constraints for the circuit. Values of the objective parameters are optimized based on the noise constraints. By using noise constraints in the optimization process, a number of performance issues can be addressed.

Abstract: A method and apparatus provide a digital circuit including dynamic logic that minimizes circuit-path delay, residue logic, and circuit area. The method and apparatus use a library of circuit cells to produce a digital circuit design using a mapping algorithm. The mapping algorithm firstly determines an arrangement of circuit cells to minimize the delay in the circuit design, secondly determines an arrangement of circuit cells to minimize the residue logic for the circuit design, thirdly determines an arrangement of circuit cells to minimize the circuit area for the circuit design, and then repeats the process for each node in the circuit until the best circuit design is produced in accordance with pre-determined criteria.

Abstract: A system and computer implemented method of modifying characteristics of a circuit provide enhanced performance. One embodiment of the method provides for determining a set of objective parameters for the circuit and receiving noise constraints for the circuit. Values of the objective parameters are optimized based on the noise constraints. By using noise constraints in the optimization process, a number of performance issues can be addressed.

Abstract: A method and apparatus provide a digital circuit including dynamic logic that minimizes circuit-path delay, residue logic, and circuit area. The method and apparatus use a library of circuit cells to produce a digital circuit design using a mapping algorithm. The mapping algorithm firstly determines an arrangement of circuit cells to minimize the delay in the circuit design, secondly determines an arrangement of circuit cells to minimize the residue logic for the circuit design, thirdly determines an arrangement of circuit cells to minimize the circuit area for the circuit design, and then repeats the process for each node in the circuit until the best circuit design is produced in accordance with pre-determined criteria.

Abstract: The present invention provides a device and method for fast SRAM reading and writing. A boost voltage source is provided, wherein the boost voltage source operates to increase a conductance of a latch device in the SRAM cell relative to a conductance of an access device in the SRAM cell. By virtue of the increased relative conductance between the latch and access devices (beta ratio), the access device may be assume a wider width without jeopardizing the read stability of the cell.

Abstract: A system and computer implemented method of modifying characteristics of a circuit provide enhanced performance. One embodiment of the method provides for determining a set of objective parameters for the circuit and receiving noise constraints for the circuit. Values of the objective parameters are optimized based on the noise constraints. By using noise constraints in the optimization process, a number of performance issues can be addressed.

Abstract: The present invention provides a device and method for fast SRAM reading and writing. A boost voltage source is provided, wherein the boost voltage source operates to increase a conductance of a latch device in the SRAM cell relative to a conductance of an access device in the SRAM cell. By virtue of the increased relative conductance between the latch and access devices (beta ratio), the access device may be assume a wider width without jeopardizing the read stability of the cell.

Abstract: A logic structure adapted to receive pulsed active input signals produces a logical output with a very small inherent switching delay. Pull-down transistors and complementary pull-up transistors are ratioed such that the default logical output level remains close to nominal even when the logic structure sinks or sources a DC current. When the pulsed input signals are inactive, no DC current path is enabled.

Abstract: A parallel self-resetting parallel binary adder provides high speed addition and subtraction. The adder combines the advantages of a fully custom design methodology with the higher performance potential of self-resetting complementary metal oxide semiconductor (CMOS) circuits. The adder logic architecture is carry look-ahead with two bit groups and requires six rows of merge logic to calculate the carry out of the Most Significant Bit (MSB). Loading on the critical path of the adder is reduced by moving as many merge blocks as possible to later rows. This allows the fan-out per stage in the critical path to be reduced from around three to two or less. The adder utilizes a bubble pipelined circuit architecture. For the adder, a bubble pipe segment consists of a row of self-resetting circuit blocks.

Abstract: A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting.

Abstract: A storage latch comprising a gate insulating layer over the substrate, shallow trenches formed through the insulating layer and in the substrate to provide device insulation; and doped regions in the substrate between the shallow trenches. The doped regions define sources and drains. Gate stacks are formed over regions of oxide adjacent the doped regions. A planarized insulator is formed between the gate stacks. Openings are provided in the planarized insulator for contacts to the doped regions and the gate stacks. Conductive material fills the openings to form contacts for the doped regions and for the gate stacks. A patterned layer of conductive material on the planarized insulator connects selected ones of the contacts for wiring portions of the latch.

Abstract: A fast comparator circuit, including a plurality of first switches operating in parallel. A first data bit from a first data word is input into a first input of each first switch, and a corresponding second data bit from a second data word is respectively input into a second input of each first switch. Each first switch provides a first logic state output when the first data bit matches the corresponding second data bit or a second logic state output when the first data bit does not match the second data bit. A plurality of second switches receive the respective logic state outputs and produce a combined output, indicating an all match or a mismatch, to a third switch combination connected to a first branch node and a second branch node to create a first voltage difference between the first and second branch nodes when an all match output results and a second voltage difference between the first and second branch node when a mismatch output results.

Abstract: A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting.

Abstract: A circuit incorporating a clocked first stage and unlocked second and third stages with amplification for driving capacitance loads with the output nodes each coupling its changed state back to the earlier stages to reset them independent of the clock. The circuit may use complementary metal-oxide semiconductor devices of various gate widths.