Patents by Inventor Bardia ZANDIAN

Bardia ZANDIAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11886259
    Abstract: A method by a computing system associated with a set of disjoint devices that includes at least one wearable device includes receiving a request to perform a task. The method further includes determining, based on sensor data associated with the set of disjoint devices, a thermal-constraint differential for each device of the set of disjoint devices. The method further includes determining a plurality of workload assignments needed to be performed to accomplish the task. The method further includes distributing, based on the thermal-constraint differentials of the set of disjoint devices, the plurality of workload assignments to one or more devices of the set of disjoint devices to satisfy one or more power or thermal constraints associated with each device of the set of disjoint devices. The method further includes performing the task by causing the one or more devices to execute the distributed plurality of work assignments.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: January 30, 2024
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Bardia Zandian, Eugene Gorbatov, Pankaj Raghuvanshi, Shrirang Madhav Yardi
  • Publication number: 20240015938
    Abstract: An artificial reality device has a component, which component is configured to enable a visual associated with artificial reality programs to a user, as well as at least one heat source and a contact point. The contact point is specially configured to accommodate an accessory, which accessory is specially configured to extend the thermal headroom of the artificial reality device.
    Type: Application
    Filed: April 25, 2023
    Publication date: January 11, 2024
    Inventors: Bardia Zandian, Alex Ockfen, Pankaj Raghuvanshi
  • Publication number: 20230168729
    Abstract: Systems and methods for peak power control include control circuitry which identifies a condition for a device. The control circuitry can apply the condition for the device to one or more models maintained for a plurality of device processing units of the device to determine one or more performance characteristics for the plurality of processing units. The control circuitry can distribute power credits to the plurality of device processing units of the device according to the determined performance characteristics for the plurality of device processing units, to manage a respective peak power for each respective device processing unit according to a number of the power credits distributed to the respective device processing unit.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 1, 2023
    Inventors: Vlad Fruchter, Nishant Sitapara, Javid Jaffari, Shrirang Madhav Yardi, Bardia Zandian
  • Publication number: 20230112115
    Abstract: A method by a computing system associated with a set of disjoint devices that includes at least one wearable device includes receiving a request to perform a task. The method further includes determining, based on sensor data associated with the set of disjoint devices, a thermal-constraint differential for each device of the set of disjoint devices. The method further includes determining a plurality of workload assignments needed to be performed to accomplish the task. The method further includes distributing, based on the thermal-constraint differentials of the set of disjoint devices, the plurality of workload assignments to one or more devices of the set of disjoint devices to satisfy one or more power or thermal constraints associated with each device of the set of disjoint devices. The method further includes performing the task by causing the one or more devices to execute the distributed plurality of work assignments.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 13, 2023
    Inventors: Bardia Zandian, Eugene Gorbatov, Pankaj Raghuvanshi, Shrirang Madhav Yardi
  • Patent number: 11106261
    Abstract: Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 31, 2021
    Assignee: NVIDIA CORPORATION
    Inventors: Aniket Naik, Siddharth Bhargav, Bardia Zandian, Narayan Kulshrestha, Amit Pabalkar, Arvind Gopalakrishnan, Justin Tai, Sachin Satish Idgunji
  • Publication number: 20200142466
    Abstract: Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.
    Type: Application
    Filed: November 2, 2018
    Publication date: May 7, 2020
    Inventors: Aniket Naik, Siddharth Bhargav, Bardia Zandian, Narayan Kulshrestha, Amit Pabalkar, Arvind Gopalakrishnan, Justin Tai, Sachin Satish Idgunji
  • Patent number: 8631290
    Abstract: An automated guardband compensation system automatically compensates for degradation in the guardband of a clocked data processing circuit while that circuit is connected within a data processing system. A control circuit automatically and repeatedly requests: a switching circuit to switch a critical path within the clocked data processing circuit out of a data processing pathway within the data processing system while the clocked data processing circuit is connected within the data processing system; a guardband test circuit to test the guardband of the critical path while the critical path is switched out of the data processing pathway; a guardband compensation circuit to increase the guardband when the results of the test indicate a material degradation in the guardband; and a switching circuit to switch the critical path back into the data processing pathway after the test.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 14, 2014
    Assignee: University of Southern California
    Inventors: Bardia Zandian, Murali Annavaram
  • Publication number: 20120159276
    Abstract: An automated guardband compensation system may automatically compensate for degradation in the guardband of a clocked data processing circuit while that circuit is connected within a data processing system. A control circuit may automatically and repeatedly request: a switching circuit to switch a critical path within the clocked data processing circuit out of a data processing pathway within the data processing system while the clocked data processing circuit is connected within the data processing system; a guardband test circuit to test the guardband of the critical path while the critical path is switched out of the data processing pathway; a guardband compensation circuit to increase the guardband when the results of the test indicate a material degradation in the guardband; and a switching circuit to switch the critical path back into the data processing pathway after the test.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 21, 2012
    Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Bardia ZANDIAN, Murali ANNAVARAM