Abstract: A translinear amplifier is disclosed. A loop amplifier drives the bases of the input and output transistor pairs from the differential collector voltage of the input pair. The loop amplifier contains a third differential pair (a gain pair). The tail current of the gain pair is inversely related to the tail current of the input pair, such that loop amplifier gain remains stable when the transconductance of the input pair changes (due, e.g., to input gain changes). In one embodiment, a linear-in-dB interface is provided that adjusts input pair tail current exponentially (and gain pair tail current exponentially and inversely) to linear voltage changes at a gain input.

Abstract: A squaring cell combines first and second exponential currents to approximate square law behavior. The exponential currents can be generated by current stacks having pairs of series-connected junctions. The exponential currents can be altered to change the shape of the exponential currents to better approximation true square law behavior. A multiplier combines four exponential currents to approximate a multiplication function. The exponential currents in the multiplier can be generated by current stacks that are cross-connected so as to generate two output currents, the difference of which represents the multiplication of two input signals.

Abstract: A gain-phase detector differentially processes the outputs from two logarithmic amplifiers to provide ratiometric gain measurement, thereby eliminating intercept as a parameter. Hard-limited outputs from the dual amplifiers are multiplied in a logarithmic scalable phase detector core to provide a calibrated phase measurement output. In the preferred embodiment, two logarithmic amplifiers and other circuitry are co-integrated on a single substrate to provide a high degree of matching between the amplifiers, thereby canceling errors in the individual frequency responses of the individual amplifiers, extending the usable frequency response, and improving effective noise figure. Other numbers of logarithmic amplifiers can be used, and their various outputs can be added, subtracted, multiplied and combined in other manners to produce continuous products, continuous quotients, mixtures of products and quotients, etc., all of RF demodulated signals.

Abstract: A translinear amplifier is disclosed. A loop amplifier drives the bases of the input and output transistor pairs from the differential collector voltage of the input pair. The loop amplifier contains a third differential pair (a gain pair). The tail current of the gain pair is inversely related to the tail current of the input pair, such that loop amplifier gain remains stable when the transconductance of the input pair changes (due, e.g., to input gain changes). In one embodiment, a linear-in-dB interface is provided that adjusts input pair tail current exponentially (and gain pair tail current exponentially and inversely) to linear voltage changes at a gain input.

Abstract: An amplifier has an input terminal to receive an input signal. The amplifier includes a first gain stage comprising a pair of input transistors and a second gain stage to drive an output stage. The output stage provides inverting and non-inverting differential output signals on inverting and non-inverting output nodes. The amplifier may also include a feedback signal electrically connected between the inverting and non-inverting output nodes to emitters of the input transistors through a resistor network.

Abstract: A squaring cell combines first and second exponential currents to approximate square law behavior. The exponential currents can be generated by current stacks having pairs of series-connected junctions. The exponential currents can be altered to change the shape of the exponential currents to better approximation true square law behavior. A multiplier combines four exponential currents to approximate a multiplication function. The exponential currents in the multiplier can be generated by current stacks that are cross-connected so as to generate two output currents, the difference of which represents the multiplication of two input signals.

Abstract: A variable attenuation system includes a steering core that continuously steers a signal to an attenuator having multiple inputs. An embodiment having an attenuator constructed from discrete components continuously interpolates a signal between the individual inputs of the attenuator. Continuous interpolation between discrete inputs can also be used with attenuators having continuous structures. A fully integrated embodiment achieves continuous input steering by moving a carrier domain along a continuous attenuator. A separate output stage utilizes adaptive biasing to reduce unnecessary current consumption.

Abstract: A control system may be selectively operated in open loop mode, for example, during data bursts. In a power control system, the transmitted power may be selectively held at a constant level, for example, at the end of a ramp period. The forward path gain of a control system may be varied in an inverse-function manner ahead of an integrator. The slope of a measurement signal from a detector may be made to have a complementary polarity.

Abstract: A squaring cell combines first and second exponential currents to approximate square law behavior. The exponential currents can be generated by current stacks having pairs of series-connected junctions. The exponential currents can be altered to change the shape of the exponential currents to better approximation true square law behavior. A multiplier combines four exponential currents to approximate a multiplication function. The exponential currents in the multiplier can be generated by current stacks that are cross-connected so as to generate two output currents, the difference of which represents the multiplication of two input signals.

Abstract: A gain-phase detector differentially processes the outputs from two logarithmic amplifiers to provide ratiometric gain measurement, thereby eliminating intercept as a parameter. Hard-limited outputs from the dual amplifiers are multiplied in a logarithmic scalable phase detector core to provide a calibrated phase measurement output. In the preferred embodiment, two logarithmic amplifiers and other circuitry are co-integrated on a single substrate to provide a high degree of matching between the amplifiers, thereby canceling errors in the individual frequency responses of the individual amplifiers, extending the usable frequency response, and improving effective noise figure. Other numbers of logarithmic amplifiers can be used, and their various outputs can be added, subtracted, multiplied and combined in other manners to produce continuous products, continuous quotients, mixtures of products and quotients, etc., all of RF demodulated signals.

Abstract: An amplifier utilizes feedback compensation to extend bandwidth. A feedback network is coupled between an output stage and an intermediate stage. One or more resistors in the feedback network can be arranged to compensate for Early voltage effects in one or more transistors in the intermediate stage. One or more capacitors in the feedback network can be arranged to cancel the junction capacitance of one or more transistors in the intermediate stage.

Abstract: An interpolator utilizes two ranks of transistors to generate a plurality of interpolator currents within the confines of a low power supply voltage. The first rank of transistors are underdriven, thereby generating a plurality of partially switched currents having shallow Gaussian-shaped functions. The partially switched currents are then spatially amplified by the second rank of transistors to reduce the overlap of the currents from adjacent transistors. The first rank of transistors are driven ratiometrically by the difference of two control currents, thereby eliminating errors caused by inaccurate resistors and current sources. A biasing op-amp senses the interpolator currents and servos the first rank of transistors, thereby regulating the interpolator currents to a value determined by a reference voltage which is temperature compensated. Thus, the biasing op-amp automatically compensates for temperature variations and manufacturing uncertainties in devices throughout the entire interpolator.

Abstract: An amplifier utilizes feedback compensation to extend bandwidth. A feedback network is coupled between an output stage and an intermediate stage. One or more resistors in the feedback network can be arranged to compensate for Early voltage effects in one or more transistors in the intermediate stage. One or more capacitors in the feedback network can be arranged to cancel the junction capacitance of one or more transistors in the intermediate stage.

Abstract: An RMS-to-DC converter implements the difference-of-squares function by utilizing two identical squaring cells operating in opposition to generate two signals. An error amplifier nulls the difference between the signals. When used in a measurement mode, one of the squaring cells receives the signal to be measured, and the output of the error amplifier, which provides a measure of the RMS value of the input signal, is connected to the input of the second squaring cell, thereby closing the feedback loop around the second squaring cell. When used in a control mode, a set-point signal is applied to the second squaring cell, and the output of the error amplifier is used to control a variable-gain device such as a power amplifier which provides the input to the first squaring cell, thereby closing the feedback loop around the first squaring cell.

Abstract: An input system for a variable gain amplifier using a continuously interpolated attenuator includes a plurality of gm stages in which the collector current from one transistor in each gm stage is diverted to AC ground, thereby eliminating a feedforward path and providing flat frequency response at very high frequencies. An additional feedforward path through the parasitic emitter capacitances in each gm stage is eliminated by a filter capacitor coupled the common emitter node of each gm stage. A compensation transistor included in each gm stage provides a differential output signal which can be used to cancel common mode feedforward signals which are coupled to the output through the collector-junction capacitances of the gm stages. The effects of parasitic capacitances are further reduced by reverse biasing the gm stages that are off.

Abstract: An RMS-DC converter generates a series of progressively amplified signal pairs which are then multiplied and weighted in such a way as to cancel uncorrelated noise while still providing true square-law response. The converter includes two series of gain stages for generating the amplified signal pairs, and a series of four-quadrant multipliers for multiplying and weighting the amplified signal pairs in response to a series of weighting signals. The outputs from the multipliers are summed and averaged, and a final output signal is generated by integrating the difference between the averaged signal and a reference signal. To preserve the square-law response over a wide range of input voltages, the system is servoed by feeding the final output signal back to an interpolator which generates the weighting signals as a series of continuously interpolated, overlapping, Gaussian-shaped current pulses having a centroid that moves along the length of the interpolator as the final output signal varies.

Abstract: An interpolator utilizes two ranks of transistors to generate a plurality of interpolator currents within the confines of a low power supply voltage. The first rank of transistors are underdriven, thereby generating a plurality of partially switched currents having shallow Gaussian-shaped functions. The partially switched currents are then spatially amplified by the second rank of transistors to reduce the overlap of the currents from adjacent transistors. The first rank of transistors are driven ratiometrically by the difference of two control currents, thereby eliminating errors caused by inaccurate resistors and current sources. A biasing op-amp senses the interpolator currents and servos the first rank of transistors, thereby regulating the interpolator currents to a value determined by a reference voltage which is temperature compensated. Thus, the biasing op-amp automatically compensates for temperature variations and manufacturing uncertainties in devices throughout the entire interpolator.

Abstract: An input system for a variable gain amplifier using a continuously interpolated attenuator includes a plurality of gm stages in which the collector current from one transistor in each gm stage is diverted to AC ground, thereby eliminating a feedforward path and providing flat frequency response at very high frequencies. An additional feedforward path through the parasitic emitter capacitances in each gm stage is eliminated by a filter capacitor coupled the common emitter node of each gm stage. A compensation transistor included in each gm stage provides a differential output signal which can be used to cancel common mode feedforward signals which are coupled to the output through the collector-junction capacitances of the gm stages. The effects of parasitic capacitances are further reduced by reverse biasing the gm stages that are off.

Abstract: An analog multiplier circuit utilizes a dual feedback structure, in which two multiplier core sections can be progressively enabled or disabled to varying degrees, thereby providing variable gain while maintaining constant bandwidth. The multipliers are preferably controlled by a pair of ratiometric gain control signals in a manner that provides very accurate end-point gain. A summing device combines the outputs from the multipliers to generate a final output signal that is buffered and fed back to the multipliers through two separate feedback paths. The circuit can operate as a video keyer that linearly selects between two input signals applied to the multipliers. Alternatively, the circuit can be operated as a variable gain amplifier (two quadrant multiplier) when one of the two inputs is not used. Each of the multipliers is preferably implemented with sets of differential transistor pairs having complementary symmetry and a Class AB current conveyor input.

Abstract: A low noise amplifier in accordance with the present invention provides extended dynamic range by sequentially interpolating an array of commonly connected gain stages. The gain stage at one end of the array has a small input signal range, but very low noise. Moving along the array, the gain stages have progressively wider input signal range, but higher noise. By sequentially enabling and disabling the gain stages with an interpolator, the amplifier can provide very low noise operation, while still accommodating larger signals when necessary. Continuous interpolation techniques are preferably utilized to provide smooth transitions between stages. The outputs from the gain stages are coupled to a loading network which is preferably weighted such that the overall gain remains constant regardless of which gain stage is enabled. A buffer amplifier and shunt feedback network provide active impedance matching.