Abstract: Embodiments of the invention include a test and measurement device, system, and method for synchronizing measurement views and configuration parameters across multiple input channels or devices. A method includes receiving signals under test associated with multiple input channels of the test and measurement instrument or with multiple devices, selecting a measurement view of one input signal or device, receiving a synchronized view enable preference from a user control interface, and synchronizing the measurement view or configuration parameters of the other signals or devices with what was chosen on the first signal or device. A test and measurement instrument includes input terminals to receive the input signals, a user control interface to receive input from an operator, a display to provide measurement information about the input signals, and a synchronization control unit to synchronize measurement views and/or configuration parameters between the inputs or devices.

Abstract: A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal, derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. A subtractor then subtracts the digital phase-locked loop feedback from the linear ramp to provide the input to the loop filter.

Abstract: A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. The digital phase-locked loop feedback is subtracted from the linear ramp to provide the input to the loop filter.

Abstract: A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal, such as a sine wave, derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. A subtractor is then used to subtract the digital phase-locked loop feedback from the linear ramp to provide the input to the loop filter.

Abstract: Embodiments of the invention include a test and measurement device, system, and method for synchronizing measurement views and configuration parameters across multiple input channels or devices. A method includes receiving signals under test associated with multiple input channels of the test and measurement instrument or with multiple devices, selecting a measurement view of one input signal or device, receiving a synchronized view enable preference from a user control interface, and synchronizing the measurement view or configuration parameters of the other signals or devices with what was chosen on the first signal or device. A test and measurement instrument includes input terminals to receive the input signals, a user control interface to receive input from an operator, a display to provide measurement information about the input signals, and a synchronization control unit to synchronize measurement views and/or configuration parameters between the inputs or devices.

Abstract: Aspects of the present invention are related, in general, to Type-III phase-locked loops. In particular, aspects of the present invention relate to analog Type-III phase-locked loop arrangements comprising at least two signal paths, wherein each signal path may correspond to a bandwidth partition and may be selected by a selector according to a bandwidth parameter value. According to one aspect of the present invention, a first signal path may correspond to a fast loop (wide closed-loop bandwidth), and a second signal path may correspond to a slow loop (narrow closed-loop bandwidth).

Abstract: Aspects of the present invention are related, in general, to Type-III phase-locked loops. In particular, aspects of the present invention relate to analog Type-III phase-locked loop anangements comprising at least two signal paths, wherein each signal path may correspond to a bandwidth partition and may be selected by a selector according to a bandwidth parameter value. According to one aspect of the present invention, a first signal path may correspond to a fast loop (wide closed-loop bandwidth), and a second signal path may correspond to a slow loop (narrow closed-loop bandwidth).

Abstract: A system and method are provided to generate a histogram of jitter peak values within histogram hardware. The histogram is then transferred to a jitter analyzer, which is implemented in either dedicated hardware or software running on a general purpose processor. The jitter analyzer calculates a cumulative distribution function (CDF) array and a complementary cumulative distribution function (CCDF) array based upon the histogram, and determines the peak jitter values based upon a probability value.

Abstract: A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal, such as a sine wave, derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. A subtractor is then used to subtract the digital phase-locked loop feedback from the linear ramp to provide the input to the loop filter.

Abstract: An automatic equalizer has a circuit for sensing cable effects that generates a control signal for a variable equalizer. A digital signal from a transmission channel is input to the variable equalizer to produce an equalized digital signal as a function of the control signal. The equalized digital signal is input to the sensing circuit which detects over-shoot or under-shoot of transitions in the equalized digital signal and adjusts the control signal accordingly to produce a balance in the transitions.

Abstract: A dual function peak metering circuit provides both monitoring and measuring functions for a composite signal having both modulated and unmodulated components. A full-wave rectified version of the composite signal is input to an envelope detector that drives a peak weighting circuit and a variable limiter. The output of the peak weighting circuit controls a threshold level for the variable limiter. The peaks of the signal at the output of the variable limiter are detected with an instantaneous peak-hold circuit that is periodically sampled and reset under microprocessor control. The microprocessor then displays the sampled value both graphically and numerically.

Abstract: Apparatus for correcting astigmatism produced by the electromagnetic deflection yoke of a cathode-ray-tube includes plural stigmator electrodes provided with elongated slots through which the cathode-ray-tube's electron beam passes. Appropriate correction voltages, stored in digital memory, are applied to the stigmator and focus electrodes for bringing about re-focusing of the electron beam in appropriate axes for restoring a single point focus on the cathode-ray-rube's screen.

Abstract: A dynamic signal shaper for a cathode ray tube display system is described. In some cathode ray tubes an electromagnetic lens is driven by a correction signal derived from the beam deflection signals. The required correction signal is proportional to the product of the squares of the horizontal and vertical deflection signals. The described signal shaper incorporates means for making the constant of proportionality independently adjustable for beam deflections in each corner of cathode ray tube screen.

Abstract: A digital electron optics correction circuit for correcting the focus and astigmatism in a displayed image on a CRT is disclosed. The circuit includes a clock generator for generating a selected number of pulses between each horizontal blanking synchronization pulse. These clock pulses are then counted by an X-address counter and a first address signal is generated corresponding to a particular horizontal position on the CRT screen for each count of the X-address counter. A pulse generator circuit is also provided which is coupled to receive the vertical blanking synchronization pulses and which provides a selected number of output pulses for each vertical blanking synchronization pulse. A Y-address counter counts the output pulses from the pulse generator circuit and provides a second address signal corresponding to a particular vertical position on the CRT screen for each count.

Abstract: A resonant magnetic deflection circuit is disclosed for reducing a retrace period of an electron beam scanning within a cathode ray tube (CRT) apparatus. Opposite polarity flyback voltage pulses occur at both ends of a deflection coil. As a result, an effective retrace voltage appearing across the deflection coil is approximately doubled, thereby reducing the retrace period of the electron beam scanning within the CRT apparatus. One end of the deflection coil is connected to a reference level source through a first parallel circuit and an S-correction capacitor, the other end thereof being connected to the reference level source through a second parallel circuit. The first and second parallel circuits comprise switching devices, damper diodes and retrace capacitors. Moreover, both ends of the deflection coil are connected to a power supply through a flyback transformer.

Abstract: A dynamic focus system for a cathode ray tube display system is described. In some cathode ray tubes an electrostatic or electromagnetic stigmator is driven by a correction signal derived from the beam deflection signals. The required signal is proportional to the product of the horizontal and vertical deflection signals. The described system incorporates a means for making the constant of proportionality independently adjustable for each quadrant of the cathode ray tube screen.