Patents by Inventor Barry J. Arnold
Barry J. Arnold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8467489Abstract: A data clock recovery system is provided. A phase detector is configured to sample an input data stream by way of a data clock and a second clock to generate a first signal indicating whether a data clock lags or leads a preferred phase of the data clock in relation to an input data stream. A phase controller is configured to process the first signal to shift a phase of the second clock toward a second preferred phase, and to shift a phase of the data clock toward the first preferred phase after the shifting of the phase of the second clock.Type: GrantFiled: August 24, 2005Date of Patent: June 18, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Dacheng (Henry) Zhou, Barry J. Arnold
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Publication number: 20120191952Abstract: Methods and apparatuses are provided for increased efficiency and enhanced power saving in a processor via scalar code optimization. The method comprises determining that an instruction comprises a scalar instruction and then processing the instruction using only a lower portion of an XMM register. The apparatus comprises an operational unit capable of determining whether an instruction comprises a scalar instruction and execution units responsive that determining for processing the scalar instruction using only a lower portion of an XMM register of the processor. By not processing the upper portion of the XMM register efficiency is increased and power saving is enhanced.Type: ApplicationFiled: January 21, 2011Publication date: July 26, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Jay E. FLEISCHMAN, Matthew M. CRUM, Kelvin GOVEAS, Michael D. ESTLICK, Barry J. ARNOLD, Ranganathan SUDHAKAR, Betty A. MCDANIEL
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Publication number: 20120005459Abstract: Methods and apparatuses are provided for increasing processor performance and energy saving via eliminating physical data movement to accomplish a move instruction. The apparatus comprises a first plurality of available physical registers mapped to a second plurality of logical registers, including a source logical register and a destination logical register. A renaming unit remaps the destination logical register to the same physical register mapping as the source logical register in response to a move instruction. In this way, the move instruction is effectively executed without moving data between physical registers. A method is provided for increasing processor performance and energy saving via eliminating physical data movement to accomplish a move instruction.Type: ApplicationFiled: December 28, 2010Publication date: January 5, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Jay FLEISCHMAN, Matthew M. CRUM, Michael ESTLICK, Ranganathan SUDHAKAR, Emil TALPES, Ganesh VENKATARAMANAN, Barry J. Arnold, Michael Sedmak
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Patent number: 7356674Abstract: A method of, and apparatus for, interfacing the hardware of a processor capable of processing instructions from more than one type of instruction set. More particularly, an engine responsible for fetching native instructions from a memory subsystem (such as an EM fetch engine) is interfaced with an engine that processes emulated instructions (such as an x86 engine). This is achieved using a handshake protocol, whereby the x86 engine sends an explicit fetch request signal to the EM fetch engine along with a fetch address. The EM fetch engine then accesses the memory subsystem and retrieves a line of instructions for subsequent decode and execution. The EM fetch engine sends this line of instructions to the x86 engine along with an explicit fetch complete signal. The EM fetch engine also includes a fetch address queue capable of holding the fetch addresses before they are processed by the EM fetch engine. The fetch requests are processed such that more than one fetch request may be pending at the same time.Type: GrantFiled: November 21, 2003Date of Patent: April 8, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Anuj Dua, James E McCormick, Jr., Stephen R. Undy, Barry J Arnold, Russell C Brockmann, David Carl Kubicek, James Curtis Stout
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Patent number: 7202702Abstract: A signal generated by circuitry for an output buffer is identified relative to a clock signal to control a slew rate of the circuitry for an output buffer.Type: GrantFiled: December 10, 2003Date of Patent: April 10, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Barry J. Arnold, Kenneth Koch, II, Philip L. Barnes
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Patent number: 7161379Abstract: One disclosed method comprises drawing current from a termination voltage supply and through a termination voltage delivery network by termination circuitry in response to a first signal on one or more lines terminated by the termination circuitry, shunting current from the termination voltage supply and through the termination voltage delivery network in response to a second signal on one or more terminated lines, and helping to reduce the shunted current for extended shunting.Type: GrantFiled: April 14, 2004Date of Patent: January 9, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Barry J. Arnold, Kevin M. Laake, Andrew R. Allen
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Patent number: 7113000Abstract: An integrated circuit is configured as a selected one of a terminated and a non-terminated bus agent for terminating a bus signal line. Reference level selection logic selects one of a first and a distinct second reference level as a selected level. The integrated circuit compares the bus signal line with the selected level to determine the state of the bus signal line.Type: GrantFiled: December 10, 2003Date of Patent: September 26, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventor: Barry J. Arnold
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Patent number: 7088130Abstract: An apparatus includes termination circuitry to terminate one or more lines. The termination circuitry draws a first current from a termination voltage supply through a termination voltage delivery network for each terminated line carrying a first signal. Partial current shunt circuitry draws a second current from the termination voltage supply through the termination voltage delivery network for each terminated line carrying a second signal. The first and second currents are distinct.Type: GrantFiled: October 3, 2005Date of Patent: August 8, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventor: Barry J. Arnold
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Patent number: 7057415Abstract: One or more characteristics of circuitry for an output buffer are identified relative to a reference a plurality of times to produce a sequence of results. One or more compensation signals for one or more output buffers are generated based on results satisfying one or more conditions.Type: GrantFiled: December 10, 2003Date of Patent: June 6, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Andrew R. Allen, Barry J. Arnold
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Patent number: 6986087Abstract: An embodiment of this invention provides a circuit and method for improving the testability of I/O driver/receivers. First, two separate I/O driver/receiver pads are electrically connected. A bit pattern generator in one of the I/O driver/receivers drives a bit pattern through a driver to the connected pads. The bit pattern is then driven through the receiver of a second I/O driver/receiver to a first clocked register. An identical bit pattern generator in the second I/O driver/receiver then drives an identical bit pattern into a second clocked register. A comparator compares the outputs of these two registers. If the two bit patterns don't match, the comparator signals there is a functional problem with one of the I/O driver/receivers.Type: GrantFiled: September 9, 2002Date of Patent: January 10, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kevin Laake, Navin Ghisiawan, Barry J. Arnold
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Patent number: 6970011Abstract: Termination circuitry is to terminate one or more lines and is to draw current from a termination voltage supply and through a termination voltage delivery network. Partial termination voltage current shunting may be used to help define a range of current variation through the termination voltage delivery network.Type: GrantFiled: November 28, 2003Date of Patent: November 29, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventor: Barry J. Arnold
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Publication number: 20040107335Abstract: A method of, and apparatus for, interfacing the hardware of a processor capable of processing instructions from more than one type of instruction set. More particularly, an engine responsible for fetching native instructions from a memory subsystem (such as an EM fetch engine) is interfaced with an engine that processes emulated instructions (such as an x86 engine). This is achieved using a handshake protocol, whereby the x86 engine sends an explicit fetch request signal to the EM fetch engine along with a fetch address. The EM fetch engine then accesses the memory subsystem and retrieves a line of instructions for subsequent decode and execution. The EM fetch engine sends this line of instructions to the x86 engine along with an explicit fetch complete signal. The EM fetch engine also includes a fetch address queue capable of holding the fetch addresses before they are processed by the EM fetch engine. The fetch requests are processed such that more than one fetch request may be pending at the same time.Type: ApplicationFiled: November 21, 2003Publication date: June 3, 2004Inventors: Anuj Dua, James E. McCormick, Stephen R. Undy, Barry J. Arnold, Russell C. Brockmann, David Carl Kubicek, James Curtis Stout
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Publication number: 20040049721Abstract: An embodiment of this invention provides a circuit and method for improving the testability of I/O driver/receivers. First, two separate I/O driver/receiver pads are electrically connected. A bit pattern generator in one of the I/O driver/receivers drives a bit pattern through a driver to the connected pads. The bit pattern is then driven through the receiver of a second I/O driver/receiver to a first clocked register. An identical bit pattern generator in the second I/O driver/receiver then drives an identical bit pattern into a second clocked register. A comparator compares the outputs of these two registers. If the two bit patterns don't match, the comparator signals there is a functional problem with one of the I/O driver/receivers.Type: ApplicationFiled: September 9, 2002Publication date: March 11, 2004Inventors: Kevin Laake, Navin Ghisiawan, Barry J. Arnold
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Patent number: 6678817Abstract: A method of, and apparatus for, interfacing the hardware of a processor capable of processing instructions from more than one type of instruction set. More particularly, an engine responsible for fetching native instructions from a memory subsystem (such as an EM fetch engine) is interfaced with an engine that processes emulated instructions (such as an x86 engine). This is achieved using a handshake protocol, whereby the x86 engine sends an explicit fetch request signal to the EM fetch engine along with a fetch address. The EM fetch engine then accesses the memory subsystem and retrieves a line of instructions for subsequent decode and execution. The EM fetch engine sends this line of instructions to the x86 engine along with an explicit fetch complete signal. The EM fetch engine also includes a fetch address queue capable of holding the fetch addresses before they are processed by the EM fetch engine. The fetch requests are processed such that more than one fetch request may be pending at the same time.Type: GrantFiled: February 22, 2000Date of Patent: January 13, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Anuj Dua, James E McCormick, Jr., Stephen R. Undy, Barry J Arnold, Russell C Brockmann, David Carl Kubicek, James Curtis Stout
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Patent number: 6560737Abstract: Circuitry for scanning and observing domino CMOS logic or other logic gates. Master and slave stages includes circuitry for latching a bit into the master stage through pulsing of a clock signal and subsequently latching the bit into the slave stage through pulsing of another clock signal. The number of transistors required for scanning is minimized by using existing latch structures within the logic.Type: GrantFiled: February 16, 2000Date of Patent: May 6, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Glenn T Colon-Bonet, Samuel D Naffziger, Barry J Arnold, Thomas Justin Sullivan
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Patent number: 6377080Abstract: A logic circuit includes a dynamic logic stage driving a dynamic evaluation stage. The dynamic logic stage responds to input signals and a clock wave to derive an output signal that is a logic function of the input signals. The output signal is derived only during a first portion of each cycle of the clock wave. The evaluation stage responds to the output signal only during an initial segment of the first portion of each clock wave cycle.Type: GrantFiled: April 28, 2000Date of Patent: April 23, 2002Assignee: Hewlett-Packard CompanyInventor: Barry J Arnold
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Patent number: 5856752Abstract: A driver circuit for capacitively loaded lines. The driver circuit has both precharge/pull-low and hold-high. The capacitively loaded line is precharged during a precharge phase of a clock signal. The driver circuit is active only during a drive phase of a clock signal. The driver has a hold-up transistor that is sufficiently large to suppress noise coupled into the line during the drive phase, but is substantially smaller than what is required to make pull-up time equal to pull-down time. The driver circuit provides the low noise characteristics of push-pull but with less circuit area and line capacitance than typical push-pull driver circuits.Type: GrantFiled: September 13, 1996Date of Patent: January 5, 1999Assignee: Hewlett-Packard CompanyInventor: Barry J. Arnold
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Patent number: 5530706Abstract: A test system for a digital integrated circuit in which internal states of the integrated circuit are captured non-destructively while the digital circuit is operating at normal clock speed. Cells for capturing states are sequentially connected into shift registers. Once internal states are latched within cells, the captured states are serially shifted out a test port while the integrated circuit continues to operate. State sampling is triggered internally via a software command or externally via an external signal synchronized to an internal clock.Type: GrantFiled: October 5, 1995Date of Patent: June 25, 1996Assignee: Hewlett-Packard CompanyInventors: Don D. Josephson, Barry J. Arnold
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Patent number: 5467026Abstract: A modified pseudo-nMOS logic gate for use in systems in which quiescent current testing is desired. The load transistor of each pseudo-nMOS gate is controlled by a two-input load control gate. One input of the load control gate is connected to a global test signal and the second input of the load control gate is connected to the output of the pseudo-nMOS gate. In normal operation, the global test signal is logically true, and the load control gate has no effect on the pseudo-nMOS gate. During quiescent current testing, the global test signal is logically false and the output of the load control gate is determined by the logical output of the pseudo-nMOS gate. If the output of the pseudo-nMOS gate is logically true, the load control gate has no effect on the pseudo-nMOS gate. If the output of the pseudo-nMOS gate is logically false, the load control gate turns off the load transistor so that no static current flows through the load transistor.Type: GrantFiled: January 18, 1994Date of Patent: November 14, 1995Assignee: Hewlett-Packard CompanyInventor: Barry J. Arnold