Abstract: An apparatus and method is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.

Abstract: An electronic system is disclosed, including multiple initiators and one or more targets coupled to a bus, and a request mask control unit (RMCU). The initiators are configured to initiate requests (e.g., read requests and write requests) via the bus, and the targets are configured to receive requests from the initiators via the bus. The targets are also configured to produce multiple MaskEnable signals, wherein each of the MaskEnable signals is generated following an initial request received via the bus, and dependent on a corresponding “masking situation” within the target. Exemplary masking situations include “delayed read,” “no read buffer available,” and “no write buffer available.” The RMCU receives the MaskEnable signals and produces multiple RequestMask signals dependent upon the MaskEnable signals. One or more of the initiators are permitted to repeat requests via the bus dependent upon one or more of the RequestMask signals.

Abstract: A method and system for performing variable-sized memory coherency transactions. A bus interface unit coupled between a slave and a master may be configured to receive a request (master request) comprising a plurality of coherency granules from the master. Each snooping unit in the system may be configured to snoop a different number of coherency granules in the master request at a time. Once the bus interface unit has received a collection of sets of indications from each snooping logic unit indicating that the associated collection of coherency granules in the master request have been snooped by each snooping unit and that the data at the addresses for the collection of coherency granules snooped has not been updated, the bus interface unit may allow the data at the addresses of those coherency granules not updated to be transferred between the requesting master and the slave.

Abstract: A method and system for reducing power in a snooping cache based environment. A memory may be coupled to a plurality of processing units via a bus. Each processing unit may comprise a cache controller coupled to a cache associated with the processing unit. The cache controller may comprise a segment register comprising N bits where each bit in the segment register may be associated with a segment of memory divided into N segments. The cache controller may be configured to snoop a requested address on the bus. Upon determining which bit in the segment register is associated with the snooped requested address, the segment register may determine if the bit associated with the snooped requested address is set. If the bit is not set, then a cache search may not be performed thereby mitigating the power consumption associated with a snooped request cache search.

Abstract: A bus architecture is provided to facilitate communication between independent bus masters and independent bus slaves by having two or more bus arbiters in a system-on-chip (SOC) system. Each bus master in the system is coupled to all bus arbiters in the system, so that each bus master can access a corresponding bus slave concurrently as well as sequentially. Such concurrent communication carries not only read and/or write data but also a target address of the corresponding bus slave, thereby enabling true concurrency in data communication between bus masters and bus slaves.

Abstract: In one aspect, a method for performing clocked operations in a device includes performing, in a device, first and second operations responsive to a clock having a primary frequency f. The device is capable of performing the operations within X and Y cycles of the clock, respectively. X cycles of the clock correspond to a time interval T1 with the clock operating at the frequency f, and, accordingly, the device is capable of performing X/Y instances of the second operation within time interval T1 with the clock operating at the frequency f. During the time interval T1 at least one extra cycle of the clock is generated to reduce performance time for the first operation. An affect of the at least one extra cycle is masked with respect to the second operation, so that instances of the second operation during the interval T1 remain no greater in number than X/Y.

Abstract: The phase of a memory clock signal is adjusted by advancing and/or delaying the phase. A configuration register is used to determine the phase adjustment of the memory clock signal. The value of the configuration register can be changed through software. This flexible phase adjustment technique is valuable in meeting various timing requirements in a source synchronous memory controller.

Abstract: A flexible, software configurable DDR read data path structure provides independently programmable sample stage and sample cycle capability. It also provides the capability to independently delay a read sample stage clock to support a wider range of data and data strobe (DQS) arrival times over a broad frequency range and subsequent sample stages to compensate for any resultant read cycle compression within any source synchronous interface. An SDRAM timing register is used to control read data path structure by changing bits in the register.

Abstract: A single common symmetrical DDR read data path structure and corresponding storage addressing scheme is provided for implementing both N-bit and (N/2)-bit interfaces to a DDR memory. The read data path structure of the present invention uses a feedback loop of a lower data path to a higher data path in conjunction with the translation of the physical addressing of the data stored into a memory. The feedback loop and address translation mechanism is enabled for (N/2)-bit mode and disabled for N-bit mode. Normally, a multiplexer controlled by a static control is used to change the bit mode.

Abstract: A circuit generating memory clock with phase advance and delay capability is provided. The phase of the memory clock is controlled by adjusting the configuration register bits. The circuit allows for a high degree of control and flexibility in the memory clock generation in that the memory clock relationship with respect to the memory command and data can be adjusted independently, thereby creating the ability to effectively adjust the memory interface timings such as setup time, hold time, and memory read data access time. Specifically, 0, 90, and 180 degree phase advance ability is combined with the ability to add delay in fine increments to achieve a more granular degree of phase adjustment.

Abstract: A method of providing a value to a cache used in a computer system, by transmitting the value from a system memory device to a lower level (e.g., L2) of the cache using a system bus, acknowledging the forwarding of the address from the lower level of the cache after said transmitting of the value, and acknowledging the forwarding of the address from a higher level (e.g., on-board) of the cache, in response to said transmitting step. The acknowledging of the forwarding of the address from the higher level of the cache, can occur prior to the acknowledgment of the forwarding of the address from the lower level of the cache. The value is transmitted from the lower level of the cache to the higher level of the cache using the higher level bus, in response to said acknowledgement of the forwarding of the address from the higher level of the cache, and this latter transmission can also occur prior to said acknowledgment of the forwarding of the address from the lower level of the cache.

Abstract: A method of avoiding contention on a communications bus using an improved tri-state driver, which negates one of the internal driver signals during a restore region of the driver cycle, such that the driver cannot switch to the high state when there is poor synchronization that delays one of the internal driver signals. Restoring logic provides a first logic signal and a second logic signal. An input gate is asserted to an active level in response to the first logic signal, and gating logic conditionally enables the input gate in response to the second signal.

Abstract: A system and method for generating a synthetic clock signal in synchronism with both a high frequency clock signal and low frequency clock signal, where the rising and falling edges of the low frequency clock signal are subject to material skew. The frequency ratio between the high and low frequency clock signals is derived by sampling the low frequency clock signal at the frequency of the high frequency cloak signal. The synthesized low frequency clock signal is generated directly from the high frequency clock signal using the determined relative frequency ratio. The synthetic clock signal is also in synchronism with the low frequency clock signal. Since the synthetic clock signal is derived directly from the high frequency clock signal, it is not subject to the skew problems of the low frequency clock signal.