Abstract: An asynchronous transfer mode (ATM) switch includes a switch memory having a plurality of discrete queues. A queue is dedicated to a connection in which a traffic stream is transmitted in cells and an inverse multiplex ATM (IMA) format. A switch controller is operable to receive a plurality of cells, to identify cells for the connection, to queue cells for the connection in the queue based on order information received with the cells, to reconstitute from the queue the traffic stream, and to switch the traffic stream and the ATM cells.

Abstract: A method and system for transmitting traffic having disparate rate components includes receiving a plurality of traffic streams. Each traffic stream includes a first component and a reduced rate second component associated with the first component. The first components of the traffic streams are segmented into successive cells. The second components of the traffic streams are distributed between a defined set of the cells for in-band transmission of the second components.

Abstract: A synchronous bus for a telecommunications node includes a frame repeating at a defined interval. Each frame includes a plurality of service channels. In at least one frame, a service channel individually transports traffic for a DS-0 connection. A set of service channels in the frame together transport an asynchronous transfer mode (ATM) cell.

Abstract: An asynchronous transfer mode (ATM) switch includes a switch memory having a plurality of discrete queues. A queue is dedicated to a connection in which a traffic stream is transmitted in cells and an inverse multiplex ATM (IMA) format. A switch controller is operable to receive a plurality of cells, to identify cells for the connection, to queue cells for the connection in the queue based on order information received with the cells, to reconstitute from the queue the traffic stream, and to switch the traffic stream and the ATM cells.

Abstract: A synchronous switch for a telecommunications node includes a switch interface, a switch controller, and a switch memory. The switch interface is operable to terminate a bus and to receive from the bus a frame having a plurality of time slots. The time slots are each operable to transport a traffic cell. The switch controller is operable to determine a type for each traffic cell received at the switch interface and to determine based on the type for a traffic cell an address for storing the traffic cell in the switch memory. The switch memory is operable to receive the traffic cell from the switch interface and the address for storing the traffic cell from the switch controller and to store the traffic cell at the address.

Abstract: A rate adjustable backplane includes a set of switch slots configured to receive one or more switch cards forming a switch core and a plurality of line slots each configured to receive a line card. A low speed bus couples the line slots to the set of switch slots. A high speed bus also couples the line slots to the set of switch slots. Each line slot includes a low speed connector coupled to the low speed bus and a high speed connector coupled to the high speed bus. The low speed connector is adapted to receive a mating connector of a line card to establish a low speed communication connection between the line card and the switch core. The high speed connector is adapted to receive a mating connector of the line card to establish a high speed link between the line card and the switch core.

Abstract: A method and system for distributed processing of traffic in a telecommunications node includes receiving a traffic stream at a line card of the telecommunications node. The traffic stream includes a plurality of discrete cells. The cells are forwarded from the line card to a centralized switch of the telecommunications node. The centralized switch identifies cells that are of a particular type. Cells of the particular type are returned from the centralized switch to the line card. The returned cells are processed at the line card.

Abstract: A bus for a telecommunications node includes a frame repeating at a defined interval and including a defined number of slots. Each slot includes an overhead portion identifying a type of traffic in the slot and a service traffic portion transporting traffic of the type. A first slot in at least one frame transports in the service traffic portion asynchronous traffic and routing information for the asynchronous traffic in the telecommunications node. A second slot in the frame transports synchronous traffic in the service traffic portion and has a location in the frame associated with routing information for the synchronous traffic in the telecommunications node.

Abstract: A switch card for telecommunications node includes a shared memory operable to store traffic channels. A time slot interchanger (TSI) is coupled to a first bus and to the shared memory. The TSI is operable based on predefined switching instructions to access the shared memory to stored traffic channels received from the first bus and to retrieve traffic channels for transmission on the first bus. An asynchronous transfer mode (ATM) switch is operable to switch a traffic cell based on header information in the traffic cell. A traffic converter is operable to convert traffic channels retrieved from the shared memory to traffic cells for processing by a bus fuser and to convert traffic cells to traffic channels for storage in the shared memory. The bus fuser is coupled to the shared memory through the traffic converter, the ATM switch, and a second bus.

Abstract: A system and method for transporting telephony signals across an ATM network using AAL1 while eliminating the jitter associated with the AAL1 cells. The present invention uses starve/inspect techniques to dynamically buffer the ATM frames such that jitter associated with the cells can be reduced while avoiding unneeded buffering that would cause excessive delay.

Abstract: A single ATM traffic stream is carried over a plurality of lower bandwidth media, such as T-1 or E-1 interfaces, using inverse multiplexing assisted by a prepended byte at the beginning of each ATM cell, the byte containing a key to permit recovery of the proper order of ATM cells.