Patents by Inventor Barry William Daly
Barry William Daly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230106072Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.Type: ApplicationFiled: August 19, 2022Publication date: April 6, 2023Applicant: Rambus Inc.Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
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Patent number: 11455022Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.Type: GrantFiled: August 25, 2020Date of Patent: September 27, 2022Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
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Publication number: 20210064116Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.Type: ApplicationFiled: August 25, 2020Publication date: March 4, 2021Applicant: Rambus Inc.Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
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Patent number: 10840920Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: GrantFiled: December 2, 2019Date of Patent: November 17, 2020Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Patent number: 10788882Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.Type: GrantFiled: September 18, 2018Date of Patent: September 29, 2020Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
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Publication number: 20200212917Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: ApplicationFiled: December 2, 2019Publication date: July 2, 2020Inventors: Jared L. ZERBE, Brian S. LEIBOWITZ, Hsuan-Jung SU, John Cronan EBLE, III, Barry William DALY, Lei LUO, Teva J. STONE, John WILSON, Jihong REN, Wayne D. DETTLOFF
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Patent number: 10541693Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: GrantFiled: January 8, 2019Date of Patent: January 21, 2020Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Publication number: 20190238142Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: ApplicationFiled: January 8, 2019Publication date: August 1, 2019Inventors: Jared L. ZERBE, Brian S. LEIBOWITZ, Hsuan-Jung SU, John Cronan EBLE, III, Barry William DALY, Lei LUO, Teva J. STONE, John WILSON, Jihong REN, Wayne D. DETTLOFF
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Publication number: 20190086990Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.Type: ApplicationFiled: September 18, 2018Publication date: March 21, 2019Applicant: Rambus Inc.Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
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Patent number: 10211841Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: GrantFiled: August 2, 2017Date of Patent: February 19, 2019Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Patent number: 10108246Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.Type: GrantFiled: December 23, 2016Date of Patent: October 23, 2018Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
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Publication number: 20180083642Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: ApplicationFiled: August 2, 2017Publication date: March 22, 2018Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Patent number: 9748960Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: GrantFiled: August 11, 2014Date of Patent: August 29, 2017Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Publication number: 20170205871Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.Type: ApplicationFiled: December 23, 2016Publication date: July 20, 2017Applicant: Rambus Inc.Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
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Patent number: 9568980Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.Type: GrantFiled: September 6, 2013Date of Patent: February 14, 2017Assignee: RAMBUS INC.Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
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Publication number: 20150177815Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a START memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.Type: ApplicationFiled: September 6, 2013Publication date: June 25, 2015Applicant: Rambus Inc.Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
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Publication number: 20140347108Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: ApplicationFiled: August 11, 2014Publication date: November 27, 2014Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Patent number: 8836394Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: GrantFiled: June 14, 2012Date of Patent: September 16, 2014Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Publication number: 20130249612Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: ApplicationFiled: June 14, 2012Publication date: September 26, 2013Applicant: RAMBUS INC.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff