Patents by Inventor Bart C. Thielges

Bart C. Thielges has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130013522
    Abstract: A system and method for managing property that in one embodiment provides a network-based system and method for creating, tracking and managing events, known herein as “incidents”, such as service requests, maintenance reminders and other events associated with managing property for supporting and enhancing the functions of tenant, property manager and vendor.
    Type: Application
    Filed: March 30, 2012
    Publication date: January 10, 2013
    Inventors: Bart C. Thielges, David S. George, Thomas C. Siffermann, JR.
  • Patent number: 8180661
    Abstract: A system and method for managing property that in one embodiment provides a network-based system and method for creating, tracking and managing events, known herein as “incidents”, such as service requests, maintenance reminders and other events associated with managing property for supporting and enhancing the functions of tenant, property manager and vendor.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: May 15, 2012
    Assignee: Landport Systems, Inc.
    Inventors: Bart C. Thielges, David S. George, Thomas C. Siffermann, Jr.
  • Publication number: 20020138289
    Abstract: A system and method for managing property that in one embodiment provides a network-based system and method for creating, tracking and managing events, known herein as “incidents”, such as service requests, maintenance reminders and other events associated with managing property for supporting and enhancing the functions of tenant, property manager and vendor.
    Type: Application
    Filed: August 23, 2001
    Publication date: September 26, 2002
    Inventors: Bart C. Thielges, David S. George, Thomas C. Siffermann
  • Patent number: 6120549
    Abstract: A method for designing an integrated circuit comprises the step of selecting a system-level parameterized module that performs a specified type of function. The method also includes the steps of specifying values for parameters of the selected system-level module and generating a netlist file from the selected system-level module. In one embodiment, the system-level parameterized module is selected from a family of system-level parameterized modules that each perform a particular function within different parameter ranges.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: September 19, 2000
    Assignee: Xilinx, Inc.
    Inventors: Gregory R. Goslin, Bart C. Thielges, Steven H. Kelem
  • Patent number: 5259006
    Abstract: A method is provided for eliminating hold time violations in implementing high-speed logic circuits specified in circuit configuration data includes the steps of providing a synchronizer flip-flop device or latch corresponding to every flip-flop device or latch specified in the circuit configuration data. The synchronizer flip-flop is provided immediately upstream in the data path from its corresponding original user flip-flop device. A predetermined amount of delay is added to the user's original clock and data signals. A synchronizing clock signal generator provides a delayed synchronizer clock for each master clock in the circuit which is provided to each user flip flop.
    Type: Grant
    Filed: August 20, 1991
    Date of Patent: November 2, 1993
    Assignee: Quickturn Systems, Incorporated
    Inventors: Roderick A. Price, Bart C. Thielges