Abstract: The present invention relates to a video server memory management for a video server transmitting video signals (VS) to user stations in response to control signals issued by these stations. This method includes the steps of providing a memory constituted by a plurality of random access memories (HD1/ . . . /HD4) and subdividing each of said video signals in a plurality of distinct blocks (BL1/ . . . /BLQ) each typically corresponding to less than a second of the video signal. It is further proposed to include in this method the step of storing any two blocks (BL1/ . . . /BLQ) which normally are to be consecutively retrieved from the memory in distinct random access memories (HD1/ . . . /HD4). In this way the full interactive video on demand service, giving the user stations control over the way in which the blocks are retrieved from the memory, is improved as is the rate at which a predetermined sequence of blocks is retrieved from the memory.

Abstract: A video on demand network (VODN), transmits video signals (VS) to user stations (US11, . . . , US2N) pursuant to the receipt of control signals (CS) issued by these user stations. In order to optimize the retrieval costs, this video on demand network maintains a large video library in a central video server (CS) and stores locally popular video signals in a plurality of local distributed video servers (DS1/2) from which the latter video signals are transmitted to the user stations. The video signals provided by the local distributed servers are updated from the central server based upon the changing popularity of the video signals. The present invention proposes in particular to store the video signals in the local distributed servers in random access read/write memories (HDA), e.g.

Abstract: The present invention relates to a video server (DS) for transmitting video signals (VS) to user stations in response to the receipt of control signals issued by these user stations and including a plurality (HDA) of memories (HDASA, HDASB) which are controlled by a plurality of memory controllers (OBC, SCSIC-A/B). The memory controllers are controlled based on the control signals by a server control means (DSC, PCM1/PCMN) which includes a server controller (DSC) and a plurality of program control modules (PCM1/PCMN) each of which is associated with a subset (HDA1/HDAN) of the plurality (HDA) of memories (HDASA, HDASB) and to a subset of the plurality of memory controllers (OBC, SCSIC-A/B).

Abstract: A video decoder is proposed which receives packets of video information relating to moving video images from a packet switching network. The video decoder provides for the elimination of a great deal of hardware overhead and also provides for increased flexibility compared to prior art decoders by letting the decoding process, implemented via a decoder (DEC1, DEC2), run asynchronously with respect to the display process, implemented via a display (DIS). Moreover, and also in contrast with prior art decoders, the video decoder is not explicitly synchronized to its corresponding encoder by explicitly recovering the system clock of the encoder. This is realized through buffering actions within a frame store memory (FSM) placed between the decoder (DEC1, DEC2) and the display (DIS). The variable length of such a buffer can be used to control the speed of the display process in order to prevent underflow or overflow of the latter buffer and corresponding image degradation.

Abstract: Encoder arrangement including the cascade connection of a data source (VSS), an encoder circuit (ENC) and a buffer circuit (BUFC) which is part of a preventive policing circuit (PPC) adapted to reduce the data output rate of said buffer circuit when said output rate does not satisfy a predetermined probability distribution function (CCCP/CR) of said output rate. The PPC at the end of each measurement interval measures this data output rate, determines the interval (BRI) to which the measured data output rate belongs and generates an alarm signal (AL). Via a gating arrangement (AG, GC) the alarm signal controls the connection of a clock signal (CLO/3) with a reduced output rate to the read-out input (RO) of the buffer circuit (BUFC) when for the measured interval the cell rate has to be decreased.

Abstract: An image signal (V1) is transform coded in a Discrete cosine Transform Coder (DCT) and the output coefficients thus provided are encoded in a zonal encoder (QZ). The output of QZ is inversely coded (IQZ) and substracted from the coefficients of the DCT. The resulting error is encoded in an entropy encoder. Both the zonal coder and the entropy encoder have quality inputs (TZQ, TEQ) controlling the compression factor, and have their outputs combined in a single compressed data stream (TXD3).