Abstract: According to one embodiment a microelectromechanical (MEMS) switch is disclosed. The MEMS switch includes a pulse generator to provide a low voltage source, a transformer coupled to the pulse generator to boost a voltage received from the pulse generator and a switch component coupled to the pulse generator. The switch component includes an actuation capacitor to store charge associated with the voltage received from the transformer.

Abstract: An Nth-order sigma-delta analog-to-digital converter (ADC) system having multilevel quantized feedback. A multilevel quantized feedback stage incorporates a multibit, current-mode digital-to-analog converter (DAC). In one embodiment, reference current sources for the DAC may comprise a plurality of floating-gate MOS transistors so that analog nonvolatile precision linearity trimming of the feedback DAC may be accomplished. Calibration of the DAC may be performed at a relatively low refresh rate, for example, only at instances when the sigma-delta ADC system is activated.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

Abstract: An image sensor having a well-to-substrate diode as the photodetector. In a preferred embodiment, a modern salicided (CMOS) process is utilized to manufacture the image sensor. The field oxide region above the diode junction is transparent to visible light, thus allowing the photodiode competitive quantum efficiency as compared to devices having source/drain diffusion-to-substrate photodiodes fabricated on a non-salicided process. The photodiode can be integrated as part of a sensor array with digital circuitry using a relatively unmodified digital CMOS process. Furthermore, the structure allows the optical properties of the photodiode to be engineered by modifying the well without deleterious effects, to approximate a first order, on the characteristics of a FET built in another identical well.

Abstract: A method and apparatus for selectively enabling individual sets of registers in a row of a register array. One embodiment of the present invention is a register array that has a number of registers arranged in a number of rows and columns. Each row of registers includes N sets of registers, where N is an integer greater than 1. The register array also includes a said selector and N said-selecting enable lines for each row of registers. Each enable line of the N set-selecting enable lines couple the set selector to one set of registers of the N sets of registers in each row. In other words, the set selector enables a particular set of registers (i.e., causes a particular set of registers to output their contents on their output bit lines) by providing an enable signal to the particular set of registers on the enable line that couples the set selector to the particular set of registers.

Abstract: A common centroid differential sensing apparatus for sensing the contents of registers in a register array. This differential sensing apparatus includes a first pair of differential bit lines, which traverse across the register array in a predetermined direction (e.g., traverse the length or the width of the array) along a first traversing path or a second traversing path. This differential sensing apparatus also includes a second pair of differential bit lines, which traverse across the register array in the predetermined direction along a third traversing path and a fourth traversing path. Furthermore, the bit lines of one of the pairs of differential bit lines swap every ##EQU1## from the top and the bottom of the register array and swap every ##EQU2## afterwards, while the bit line pairs of the other of the pairs of the differential bit lines swap at ##EQU3## from the top and the bottom of the register array and every ##EQU4## afterwards, where N is an integer greater than 0.