Abstract: According to one embodiment a microelectromechanical (MEMS) switch is disclosed. The MEMS switch includes a pulse generator to provide a low voltage source, a transformer coupled to the pulse generator to boost a voltage received from the pulse generator and a switch component coupled to the pulse generator. The switch component includes an actuation capacitor to store charge associated with the voltage received from the transformer.

Abstract: An Nth-order sigma-delta analog-to-digital converter (ADC) system having multilevel quantized feedback. A multilevel quantized feedback stage incorporates a multibit, current-mode digital-to-analog converter (DAC). In one embodiment, reference current sources for the DAC may comprise a plurality of floating-gate MOS transistors so that analog nonvolatile precision linearity trimming of the feedback DAC may be accomplished. Calibration of the DAC may be performed at a relatively low refresh rate, for example, only at instances when the sigma-delta ADC system is activated.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and circuit to perform an analog-to-digital conversion is provided. The method may include generating and storing a combined charge which is generated by combining an input charge and a reference charge.

Abstract: A buffer circuit includes an amplifier, a pass gate circuit and a level shifter. The pass gate circuit communicates an input signal to the amplifiers and includes a terminal to control the communication. A level shifter furnishes a control signal to the terminal of the pass gate circuit and regulates the control signal based on a magnitude of the input signal.

Abstract: A buffer circuit includes an amplifier, a pass gate circuit and a level shifter. The pass gate circuit communicates an input signal to the amplifiers and includes a terminal to control the communication. A level shifter furnishes a control signal to the terminal of the pass gate circuit and regulates the control signal based on a magnitude of the input signal.

Abstract: An analog-to-digital converter (ADC) is provided. The analog-to-digital converter includes a plurality of differential comparators. For each of the plurality of differential comparators the ADC receives differential input signals and differential reference signals and generates an output signal. The ADC also includes a self-calibration circuit to receive from each of the plurality of differential comparators the output signal. In response to the output signal, the self-calibration circuit generates a self-calibration signal. The ADC further includes an adjustable reference signal generator to provide the differential reference signals based on the self-calibration signal.

Abstract: In one embodiment, the present invention provides a circuit that includes a core circuit and a control circuit coupled to the core circuit. The control circuit reduces a leakage current in the core circuit when the core circuit is in a Sleep mode. The control circuit maintains a logic state of the core circuit when the core circuit is in a Drowsy mode.

Abstract: A method and apparatus for performing analog to digital conversion. A voltage to current converter converts an analog input voltage to an input current. A current reference generates a reference current. A plurality of scaling elements scaled the reference current to yield a plurality of scaled reference currents each corresponding to some voltage level within the dynamic range of the input voltage. The input current is compared to each of the scaled reference currents in a plurality of current comparators to generate a thermometer code from which a digital representation of the analog input voltage is derived.

Abstract: A method and apparatus for performing analog to digital conversion. A voltage to current converter converts an analog input voltage to an input current. A current reference generates a reference current. A plurality of scaling elements scaled the reference current to yield a plurality of scaled reference currents each corresponding to some voltage level within the dynamic range of the input voltage. The input current is compared to each of the scaled reference currents in a plurality of current comparators to generate a thermometer code from which a digital representation of the analog input voltage is derived.

Abstract: A current regenerative comparator. A pair of cross coupled inverters are coupled to an equalizing transistor, an input current mirror and a reference current mirror, such that current flowing in the input current mirror is compared to the current flowing in the reference current mirror.

Abstract: A speed governor for an integrated circuit which prevents the operation of the integrated circuit above a selected frequency. The speed governor generates a frequency reference and compares the frequency reference to the frequency of the external clock signal that clocks the integrated circuit. As a result of the comparison, if the frequency of the input clock signal is greater than the frequency reference then operation of the integrated circuit is disrupted.

Abstract: A multiple staged charge pump network with staggered clock phases for pumping a first voltage to a second voltage with high current capability. The charge pump includes multiple serial charge pumps connected in parallel, multi-phase clocks, input voltage and output voltage connectors. The multiple serial charge pumps have in each series a plurality of diode-connected n-channel MOSFETs. The first n-channel MOSFET in each series is coupled to the input voltage connector, while the rest of the n-channel MOSFETs are coupled to a pumping capacitor at their diode-connected gates. The clocks are coupled to the multiple serial charge pumps for generating a plurality of phases of clocks with each phase of the clocks being applied to the alternating n-channel MOSFETs in a series such that adjoining n-channel MOSFETs are not driven by the same phase of clock. The input voltage connector is coupled to the first n-channel MOSFET in each series of the multiple serial charge pump for providing an input voltage.

Abstract: A high voltage CMOS n-well switch with guarding against reverse junction breakdown, as well as gate-aided breakdown. The CMOS switch of the present invention comprises two pairs of cascoding p-channel MOSFET loads, two pairs of cascoding n-channel MOSFET drivers and an inverter for input. One device in each pair of MOSFETs is used as a guard against gate-aided breakdown. The p-channel MOSFETs have independent n-wells so that the guard devices have their n-wells independently biased without being pulled by the n-wells of the load devices. The inverter is used to provide complementary inputs to the switch. By having independent n-wells, the breakdown voltage of the switch is raised above p+/n-well reverse breakdown voltage.

Abstract: A MOS voltage trim amplifier which can multiply an input voltage with a quantized value to generate an output voltage. The MOS trim amplifier comprises a MOS op-amp, a multiplying feedback network, a gate-bias network and startup circuit. The MOS op-amp has a noninverting terminal for receiving the input and an inverting terminal for receiving the feedback network. The multiplying feedback network uses two MOSFETs as feedback elements to provide the voltage ratio for the multiplication. The gate-bias network provides a reference voltage which is a fraction of the input voltage through a MOSFET voltage divider to the feedback MOSFETs. Current mirrors are employed in the gate-bias network to provide a constant stable current through the MOSFET voltage divider to avoid loading the input. The startup circuit generates a bias current to the two feedback MOSFETs to drive them out of their natural off state.

Abstract: A MOS voltage trim amplifier which can multiply an input voltage with a quantized value to generate an output voltage. The MOS trim amplifier comprises a MOS op-amp, a multiplying feedback network, a gate-bias network and startup circuit. The MOS op-amp has a noninverting terminal for receiving the input and an inverting terminal for receiving the feedback network. The multiplying feed back network uses two MOSFETs as feedback elements to provide the voltage ratio for the multiplication. The gate-bias network provides a reference voltage which is a fraction of the input voltage through a MOSFET voltage divider to the feedback MOSFETs. Current mirrors are employed in the gate-bias network to provide a constant stable current through the MOSFET voltage divider to avoid loading the input. The startup circuit generates a bias current to the two feedback MOSFETs to drive them out of their natural off state.

Abstract: A voltage to current converter circuit manufactured with a MOS process generates a linear reference current over a wide bandwidth and operates with an input signal that varies to either supply rail. A voltage divider network scales an input voltage for conversion to a linear current by a cascode current mirror and a gain resistor. The value of the gain resistor determines the transconductance of the conversion from voltage to current. A second current mirror provides feedback to keep the reference current accurate. An output stage makes available high impedance source and sink current output terminals wherein a source current and a sink current relative to the reference current are provided. Several voltage to current converter circuits may be coupled together to provide a addition, subtraction, multiplication, and other circuit and system functions.