Abstract: Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist layer and plasma etch parameters are chosen to obtain openings with sloped sidewalls having a pre-defined slope, due to controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during etching. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric layer is planarized using chemical mechanical polishing, leading to mutually isolated contact areas. The disclosure is also related to components obtainable by the method and to a semiconductor package comprising such components.

Abstract: A semiconductor device having through-substrate vias is disclosed. In one aspect, the device includes a substrate having at least one front-end-of-line (FEOL) device and a back-end-of-line (BEOL) comprising a metal pad. The device additionally includes at least one first contact plug contacting the at least one FEOL device and at least one second contact plug underneath the metal pad and in electrical contact therewith. At least one second contact plug has one end contacting the metal pad and has other end contacting a material that is not part of a FEOL device.

Abstract: A semiconductor device having through-substrate vias is disclosed. In one aspect, the device includes a substrate having at least one front-end-of-line (FEOL) device and a back-end-of-line (BEOL) comprising a metal pad. The device additionally includes at least one first contact plug contacting the at least one FEOL device and at least one second contact plug underneath the metal pad and in electrical contact therewith. At least one second contact plug has one end contacting the metal pad and has other end contacting a material that is not part of a FEOL device.

Abstract: Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist layer and plasma etch parameters are chosen to obtain openings with sloped sidewalls having a pre-defined slope, due to controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during etching. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric layer is planarized using chemical mechanical polishing, leading to mutually isolated contact areas. The disclosure is also related to components obtainable by the method and to a semiconductor package comprising such components.

Abstract: A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips.

Abstract: A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.

Abstract: A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.

Abstract: A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.

Abstract: A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips.

Abstract: A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.

Abstract: A method for the fabrication of electrical interconnects in a substrate is disclosed. In one aspect, the method includes providing a substrate having a first main surface. The method may further include producing a ring structure in the substrate from the first main surface, which surrounds an inner pillar structure and has a bottom surface. The method may further include filling the ring structure with a dielectric material. The method may further include providing a conductive inner pillar structure, thereby forming an interconnect structure, which forms an electrical path from the bottom surface up until the first main surface. This conductive inner pillar structure can for example be provided by removing the inner pillar structure leaving a pillar vacancy and partially filling the vacancy with a conductive material. The dielectric material may be applied in liquid phase.

Abstract: A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.

Abstract: A method is disclosed for bonding two elements by means of a bonding agent such as a glue layer, wherein the bonding agent is removable, and wherein between the bonding agent and at least one element, a sacrificial layer is applied which is selectively removable with respect to that element. According to embodiments, the elements comprise a die or a substrate bonded to a carrier wafer. The nature and type of the die or substrate and of the carrier can vary within the scope of embodiments of the invention. Also disclosed is a composite substrate obtainable by methods of the invention.

Abstract: A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.

Abstract: The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.

Abstract: A method is disclosed for bonding two elements by means of a bonding agent such as a glue layer, wherein the bonding agent is removable, and wherein between the bonding agent and at least one element, a sacrificial layer is applied which is selectively removable with respect to that element. According to embodiments, the elements comprise a die or a substrate bonded to a carrier wafer. The nature and type of the die or substrate and of the carrier can vary within the scope of embodiments of the invention. Also disclosed is a composite substrate obtainable by methods of the invention.

Abstract: The invention relates to a method of optimizing an alignment strategy for processing batches of substrates in a lithographic projection apparatus. First, all substrates in a plurality of batches of substrates in the lithographic projection apparatus are sequentially aligned and exposed using a predefined alignment strategy. Then, alignment data is determined for each substrate in the plurality of batches of substrates. Next, at least one substrate in each batch of substrates is selected to render a set of selected substrates comprising at least one substrate in each batch. In a metrology tool, overlay data for each of the selected substrates is determined. Then, overlay indicator values for a predefined overlay indicator are calculated for the predefined alignment strategy and for other possible alignment strategies. In this calculation, the alignment data and the overlay data of the selected substrates is used.

Abstract: The invention relates to a method of optimizing an alignment strategy for processing batches of substrates in a lithographic projection apparatus. First, all substrates in a plurality of batches of substrates in the lithographic projection apparatus are sequentially aligned and exposed using a predefined alignment strategy. Then, alignment data is determined for each substrate in the plurality of batches of substrates. Next, at least one substrate in each batch of substrates is selected to render a set of selected substrates including at least one substrate in each batch. In a metrology tool, overlay data for each of the selected substrates is determined. Then, overlay indicator values for a predefined overlay indicator are calculated for the predefined alignment strategy and for other possible alignment strategies. In this calculation, the alignment data and the overlay data of the selected substrates is used.

Abstract: The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.

Abstract: A method according to one embodiment of the invention relates to determining at least one parameter of a model that provides information about a position of an object. The object may include a plurality of alignment marks of which desired positions are known. The method includes measuring a plurality of positional parameters for each alignment mark. Based on the measured plurality of positional parameters, which are weighted with weighing coefficients, at least one parameter of the model of the object is determined. The numerical value of each weighing coefficient is determined together with the at least one parameter of the model.