Patents by Inventor Baruch Bublil
Baruch Bublil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9137485Abstract: A home multimedia network comprises a plurality of source nodes, wherein each of the source nodes includes an apparatus for concurrently transmitting and receiving high-speed data services; a plurality of sink nodes, wherein each of the sink nodes includes the apparatus for concurrently transmitting and receiving high-speed data services; a switch for connecting a first group of the plurality of source nodes located at one room to one or more sink nodes located at a different room than the first group of source nodes, the first group of source nodes and the one or more sink nodes are connected to the switch through a twisted-pair cable, the high-speed data services are concurrently transported over the twisted-pair cable, wherein the high-speed data services include at least uncompressed multimedia data, Ethernet data, and Universal Serial Bus data.Type: GrantFiled: January 20, 2011Date of Patent: September 15, 2015Assignee: Cadence Design Systems, Inc.Inventors: Amir Bar-Niv, Baruch Bublil
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Patent number: 8107543Abstract: A diversity transmission scheme uses a number of antennas that is greater than the limitation of two transmitting antennas in the well-known Alamouti scheme. In an embodiment comprising four antennas, the antennas transmit in pairs such that each antenna transmits a block that is used in the Alamouti scheme. This increases the transmission rate. For example, the transmission of two signals at a given time slot increases transmission rate by a factor of two. The invention not only increases the number of antennas, but also increases the transmission rate. At the receiver end, the code is decoded without matrix inversion and without much noise enhancement. Moreover, noise enhancement stability is increased by a simple, partial interference cancellation scheme, that results in improved decoding performance.Type: GrantFiled: June 27, 2006Date of Patent: January 31, 2012Assignee: Amimon Ltd.Inventors: Meir Feder, Eran Doron, Baruch Bublil
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Publication number: 20110179456Abstract: A home multimedia network comprises a plurality of source nodes, wherein each of the source nodes includes an apparatus for concurrently transmitting and receiving high-speed data services; a plurality of sink nodes, wherein each of the sink nodes includes the apparatus for concurrently transmitting and receiving high-speed data services; a switch for connecting a first group of the plurality of source nodes located at one room to one or more sink nodes located at a different room than the first group of source nodes, the first group of source nodes and the one or more sink nodes are connected to the switch through a twisted-pair cable, the high-speed data services are concurrently transported over the twisted-pair cable, wherein the high-speed data services include at least uncompressed multimedia data, Ethernet data, and Universal Serial Bus dataType: ApplicationFiled: January 20, 2011Publication date: July 21, 2011Applicant: TRANSWITCH CORPORATIONInventors: Amir Bar-Niv, Baruch Bublil
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Patent number: 7724847Abstract: Techniques are described to reduce delayed reflection inter-symbol interference (ISI) in signals. In some implementations, a channel reflection canceller is provided at a signal receiver to reduce delayed reflection ISI in received signals. The channel reflection canceller may be provided with a signal from an equalizer output or a tentative or final decision from a forward-error correction (FEC) decoder. Based on the signal from the equalizer output or tentative or final decisions from the FEC decoder, the channel reflection canceller may generate a signal to reduce delayed reflection ISI in received signals. In addition or as an alternative, in some implementations, the remote transmitter of the signal generates a delayed reflection ISI reducing signal to reduce delayed reflection ISI present in the signal transmitted over a channel. The transmitter may generate the delayed reflection ISI reducing signal using information provided by the remote signal receiver.Type: GrantFiled: May 3, 2005Date of Patent: May 25, 2010Assignee: Intel CorporationInventors: Baruch Bublil, Amir Mezer
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Publication number: 20070297528Abstract: A diversity transmission scheme uses a number of antennas that is greater than the limitation of two transmitting antennas in the well-known Alamouti scheme. In an embodiment comprising four antennas, the antennas transmit in pairs such that each antenna transmits a block that is used in the Alamouti scheme. This increases the transmission rate. For example, the transmission of two signals at a given time slot increases transmission rate by a factor of two. The invention not only increases the number of antennas, but also increases the transmission rate. At the receiver end, the code is decoded without matrix inversion and without much noise enhancement. Moreover, noise enhancement stability is increased by a simple, partial interference cancellation scheme, that results in improved decoding performance.Type: ApplicationFiled: June 27, 2006Publication date: December 27, 2007Inventors: Meir Feder, Eran Doron, Baruch Bublil
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Patent number: 7245686Abstract: Signal processing apparatus, including a circuit which processes signals received on multiple channels so as to extract therefrom at least first and second sequences of symbols, and a FIFO, which receives and stores at least one bit of each of the symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval. The apparatus includes a predictor, which determines, for each of the symbols in the first interval of the first sequence an expected value of the at least one bit in a corresponding one of the second symbols in the second interval, and logic, which compares the expected value with the at least one bit of each of the second symbols in the FIFO, so as to determine a relative skew between the first and at least the second channel.Type: GrantFiled: December 16, 2002Date of Patent: July 17, 2007Assignee: Mysticom Ltd.Inventors: Rami Weiss, Baruch Bublil, Israel Greiss
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Patent number: 7170931Abstract: An equalizer, consisting of a plurality of taps, each tap having a multiplier which is coupled to multiply a respective input sample by a respective coefficient, the taps being arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The equalizer further includes an input selector, which is coupled to toggle the input sample to at least a selected tap among the plurality of taps, responsive to a state of the equalizer, so that the equalizer operates in a first state as a feed forward equalizer, and in a second state as a blind equalizer.Type: GrantFiled: December 16, 2002Date of Patent: January 30, 2007Assignee: Mysticom Ltd.Inventors: Israel Greiss, Baruch Bublil, Jeffrey Jacob, Dimitry Taich
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Patent number: 7167883Abstract: A finite impulse response filter, including a plurality of taps arranged to receive and process a sequence of input data samples so as to generate a filter output. Each tap consists of a multiplier operating in one's complement arithmetic, the multiplier being coupled to multiply a respective input sample from the sequence by a respective equalization coefficient, and an adder, which sums an output from the multiplier. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The filter also includes an adjustment-accumulator coupled to receive the filter output and responsive thereto to generate an adjustment that is adapted to correct the filter output to a twos complement result, and an adjustment-adder which sums the adjustment and the filter output to generate a final output.Type: GrantFiled: December 16, 2002Date of Patent: January 23, 2007Assignee: Mysticom Ltd.Inventors: Israel Greiss, Baruch Bublil, Jeffrey Jacob, Dimitry Taich
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Publication number: 20060251194Abstract: Techniques are described to reduce delayed reflection inter-symbol interference (ISI) in signals. In some implementations, a channel reflection canceller is provided at a signal receiver to reduce delayed reflection ISI in received signals. The channel reflection canceller may be provided with a signal from an equalizer output or a tentative or final decision from a forward-error correction (FEC) decoder. Based on the signal from the equalizer output or tentative or final decisions from the FEC decoder, the channel reflection canceller may generate a signal to reduce delayed reflection ISI in received signals. In addition or as an alternative, in some implementations, the remote transmitter of the signal generates a delayed reflection ISI reducing signal to reduce delayed reflection ISI present in the signal transmitted over a channel. The transmitter may generate the delayed reflection ISI reducing signal using information provided by the remote signal receiver.Type: ApplicationFiled: May 3, 2005Publication date: November 9, 2006Inventors: Baruch Bublil, Amir Mezer
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Patent number: 6993673Abstract: Apparatus for recovering timing of data input to a receiver, the apparatus consisting of an interpolator which receives the input data and generates interpolated-data in response to an interpolation coefficient, and a feed-forward equalizer having at least three taps. Each tap consists of a multiplier which is coupled to multiply a respective input sample by a respective adaptive equalization coefficient. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The equalizer receives and equalizes the interpolated-data so as to generate equalized-data from the interpolated-data. The apparatus also includes a timing sensor which adjusts the interpolation coefficient responsive a third adaptive equalization coefficient comprised in the equalization coefficients.Type: GrantFiled: December 16, 2002Date of Patent: January 31, 2006Assignee: Mysticom Ltd.Inventors: Israel Greiss, Baruch Bublil, Jeffrey Jacob, Dimitry Taich
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Publication number: 20030182619Abstract: Apparatus for recovering timing of data input to a receiver, the apparatus consisting of an interpolator which receives the input data and generates interpolated-data in response to an interpolation coefficient, and a feed-forward equalizer having at least three taps. Each tap consists of a multiplier which is coupled to multiply a respective input sample by a respective adaptive equalization coefficient. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The equalizer receives and equalizes the interpolated-data so as to generate equalized-data from the interpolated-data. The apparatus also includes a timing sensor which adjusts the interpolation coefficient responsive a third adaptive equalization coefficient comprised in the equalization coefficients.Type: ApplicationFiled: December 16, 2002Publication date: September 25, 2003Inventors: Israel Greiss, Baruch Bublil, Jeffrey Jacob, Dimitry Taich
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Publication number: 20030142772Abstract: Signal processing apparatus, including a circuit which processes signals received on multiple channels so as to extract therefrom at least first and second sequences of symbols, and a FIFO, which receives and stores at least one bit of each of the symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval.Type: ApplicationFiled: December 16, 2002Publication date: July 31, 2003Inventors: Rami Weiss, Baruch Bublil, Israel Greiss
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Publication number: 20030138039Abstract: An equalizer, consisting of a plurality of taps, each tap having a multiplier which is coupled to multiply a respective input sample by a respective coefficient, the taps being arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence.Type: ApplicationFiled: December 16, 2002Publication date: July 24, 2003Inventors: Israel Greiss, Baruch Bublil, Jeffrey Jacob, Dimitry Taich
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Publication number: 20030138038Abstract: A finite impulse response filter, including a plurality of taps arranged to receive and process a sequence of input data samples so as to generate a filter output. Each tap consists of a multiplier operating in ones complement arithmetic, the multiplier being coupled to multiply a respective input sample from the sequence by a respective equalization coefficient, and an adder, which sums an output from the multiplier. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence.Type: ApplicationFiled: December 16, 2002Publication date: July 24, 2003Inventors: Israel Greiss, Baruch Bublil, Jeffrey Jacob, Dimitry Taich