Abstract: A computer system includes a main processing unit (12) coupled to a DSP/memory module (40). The DSP/memory module (40) includes semiconductor memory (42) and digital signal processor circuitry (44) including one or more digital signal processors (56). The DSP/memory module (40) may be placed in standard main memory sockets, such as a SIMM or DIMM sockets, and used as conventional main memory. The memory module can also be used in a smart mode, wherein the digital signal processor (56) performs operations on data for retrieval by the main processing unit (12).

Abstract: A computer system includes a main processing unit (12) coupled to a DSP/memory module (40). The DSP/memory module (40) includes semiconductor memory (42) and digital signal processor circuitry (44) including one or more digital signal processors (56). The DSP/memory module (40) may be placed in standard main memory sockets, such as a SIMM or DIMM sockets, and used as conventional main memory. The memory module can also be used in a smart mode, wherein the digital signal processor (56) performs operations on data for retrieval by the main processing unit (12).

Abstract: A smart video memory (10) is provided that includes data storage (12 and 18), a serial access memory (19), and a processing core (14 and 16) for executing instructions stored in the data storage area (12 and 18). Externally, smart memory (10) is directly accessible as a standard video memory device.

Abstract: Memory chips with data memory (202), embedded logic (206) and broadcast memory (204) for two modes of operation are disclosed. A first mode of operation is the usual memory mode expected of a data RAM. The second mode of operation allows localized computation and/or processing of the data in data memory (202) by the embedded logic (206) with minimal handshaking with a remote CPU. In a functioning system, the memory chips are organized in a hierarchical manner and include address-associative memory systems.

Abstract: A method and system for implementing time scale modification wherein the method includes a Zero Crossing Module (22) for determining zero crossing points in the signal, a Feature Vector Module (24) for generating feature vectors describing the zero crossing points, a Distance Metric Module (26) for generating distance metrics describing local characteristics at the zero crossing points, an Alignment Module (28) for using the feature vectors and distance metrics for aligning and synchronizing the signal in accordance with local similarities and similarity over a selected time interval to generate a time scale modified signal. The present invention also includes a Cross Fade Module (20) for smoothing transitions between successive frames of the resulting time scale modified signal.

Abstract: A smart memory (10) is provided that includes data storage (12 and 18) and a processing core (14 and 16) for executing instructions stored in the data storage area (12 and 18). Externally, smart memory (10) is directly accessible as a standard memory device. In a first mode of operation, the smart memory (10) is a data storage facility for an associated central processing unit (22). In a second mode of operation, the smart memory (10) is a storage facility for the processing core (14 and 16) and for central processing unit (22) for simultaneous execution of instructions. The central processing unit (22) controls the mode of operation and determines the instructions executed by the processing core (14 and 16). The wide data bus, available with an integrated processor/storage facility, permits certain processing operations to be off-loaded to the smart memory (10) where the processing operations can be performed more efficiently.

Abstract: A Karaoke (10) apparatus with autokeying is provided by measuring the average pitch (28) of the singer or user over a predetermined time period, comparing (29) the pitch of the singer or user voice to that of a reference pitch to provide a signal representing mismatch and changing the pitch (31) of the background music to match that of the singer or user.

Abstract: A method and system are provided for improved processing between a host computer (200) and process logic (170). Data instructions are stored at multiple memory locations of a memory (150). The data are processed in response to instructions by the process logic (170), which is integrated with the memory (150) within a single integrated circuit. The memory locations are directly accessible without bus arbitration by the external device coupled to the single integrated circuit through an external interface (180), which controls the processing speed of the process logic (170).

Abstract: A method and apparatus are provided for identifying one or more boundaries of a speech pattern within an input utterance. One or more anchor patterns are defined, and an input utterance is received. An anchor section of the input utterance is identified as corresponding to at least one of the anchor patterns. A boundary of the speech pattern is defined based upon the anchor section. Also provided are a method and apparatus for identifying a speech pattern within an input utterance. One or more segment patterns are defined, and an input utterance is received. Portions of the input utterance which correspond to the segment patterns are identified. One or more of the segments of the input utterance are defined responsive to the identified portions.

Abstract: An efficient pruning method reduces central processing unit (CPU) loading during real time speech recognition by instructing the CPU to compare a current state's previously calculated probability score against a predetermined threshold value and to discard hypothesis containing states with probability scores below such threshold. After determining that the current state should be kept, the CPU is directed to locate an available slot in the scoring buffer where information about the current state is then stored. The CPU locates an available slot by comparing the current time-index with the time-index associated with each scoring buffer slot. When they are equal, the slot is considered not available; when the current time-index is greater, the slot is considered available. After the information about the current state is stored, the CPU then sets the current state's backpointer to point at the start state of the current best path if the current states represents a completed model.