Patents by Inventor Bassam S. Kamand
Bassam S. Kamand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11544199Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.Type: GrantFiled: October 12, 2021Date of Patent: January 3, 2023Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.Inventors: Bassam S. Kamand, Waleed Younis, Ramon Zuniga, Jagadish Rongali
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Patent number: 11467966Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion, a tag memory portion, and one or more peripheral circuits configured to receive a CPU address corresponding with an address of the RAM memory storing a particular CPU instruction. The one or more peripheral circuits are configured to receive a way quantity indication indicating of a number of ways into which the instruction memory portion and the tag memory portion are to be subdivided, the one or more peripheral circuits are configured to identify which bits of the CPU address form the tag portion based on the way quantity indication, and the one or more peripheral circuits are configured to determine whether the particular CPU instruction is stored in the cache memory based on the identified tag portion of the CPU address and tag data stored in the cache memory.Type: GrantFiled: September 2, 2020Date of Patent: October 11, 2022Assignee: Shenzhen Goodix Technology Co., Ltd.Inventor: Bassam S Kamand
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Publication number: 20220066942Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.Type: ApplicationFiled: October 12, 2021Publication date: March 3, 2022Inventors: Bassam S. Kamand, Waleed Younis, Ramon Zuniga, Jagadish Rongali
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Publication number: 20220066933Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion, a tag memory portion, and one or more peripheral circuits configured to receive a CPU address corresponding with an address of the RAM memory storing a particular CPU instruction. The one or more peripheral circuits are configured to receive a way quantity indication indicating of a number of ways into which the instruction memory portion and the tag memory portion are to be subdivided, the one or more peripheral circuits are configured to identify which bits of the CPU address form the tag portion based on the way quantity indication, and the one or more peripheral circuits are configured to determine whether the particular CPU instruction is stored in the cache memory based on the identified tag portion of the CPU address and tag data stored in the cache memory.Type: ApplicationFiled: September 2, 2020Publication date: March 3, 2022Inventor: Bassam S Kamand
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Patent number: 11188465Abstract: A cache memory is disclosed. The cache memory includes a plurality of ways, each way including an instruction memory portion, where the instruction memory portion includes a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a controller configured to determine that each of a predetermined number of cache memory hit conditions have occurred, and a replacement policy circuit configured to identify one of the plurality of ways as having experienced a fewest quantity of hits of the predetermined number of cache memory hit conditions, where the controller is further configured to determine that a cache memory miss condition has occurred, and, in response to the miss condition, to cause instruction data retrieved from a RAM memory to be written to the instruction memory portion of the way identified by the replacement policy circuit.Type: GrantFiled: September 2, 2020Date of Patent: November 30, 2021Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.Inventor: Bassam S Kamand
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Patent number: 11176051Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.Type: GrantFiled: March 13, 2020Date of Patent: November 16, 2021Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.Inventors: Bassam S. Kamand, Waleed Younis, Ramon Zuniga, Jagadish Rongali
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Publication number: 20210286732Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.Type: ApplicationFiled: March 13, 2020Publication date: September 16, 2021Inventors: Bassam S. Kamand, Waleed Younis, Ramon Zuniga, Jagadish Rongali
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Patent number: 10866612Abstract: A clock generation circuit is disclosed. The clock generation circuit includes a logic gate configured to, in response to a control input receiving a first control signal, generate an output clock based on a first input clock received by a first identified clock input. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on a fixed logic level. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on the second input clock.Type: GrantFiled: June 23, 2020Date of Patent: December 15, 2020Assignee: Goodix Technology Inc.Inventors: Bassam S. Kamand, Ramon Zuniga, Perry Virjee
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Patent number: 10739813Abstract: A clock generation circuit is disclosed. The clock generation circuit includes a logic gate configured to, in response to a control input receiving a first control signal, generate an output clock based on a first input clock received by a first identified clock input. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on a fixed logic level. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on the second input clock.Type: GrantFiled: March 13, 2020Date of Patent: August 11, 2020Assignee: GOODIX TECHNOLOGY INC.Inventors: Bassam S. Kamand, Ramon Zuniga, Perry Virjee