Abstract: A system, method, and computer program product for cell-aware fault model generation. Embodiments determine defects of interest for a cell, typically from cell layout and a transistor-level cell netlist. A circuit simulator performs analog fault simulation on the transistor-level netlist to determine detectable defects from the defects of interest, and detection conditions for the detectable defects. The circuit simulator employs fault sensitivity analysis (FSA) for amenable cells for greatly accelerated fault detection. Embodiments generate and output cell-aware fault models for the detectable defects from the detection conditions, for use in automated test pattern generation.