Abstract: Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.

Abstract: A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

Abstract: In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current magnitude varies from one write loop to another.

Abstract: Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.

Abstract: A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

Abstract: A semiconductor memory device having an efficient core structure for multi-writing includes a data input/output line, a plurality of memory banks each comprising a plurality of memory cells, a first global bit line and a second global bit line which are shared by the plurality of memory banks, and a first write driver and a second write driver which are connected with the data input/output line and provide a program current to the plurality of memory banks through the first and second global bit lines, respectively. Each memory bank includes a first cell area connected with the first global bit line and a second cell area connected with the second global bit line.

Abstract: A semiconductor memory device includes at least one write global bit line connected to a plurality of local bit lines and at least one read global bit line connected to the local bit lines. The phase-change memory device having the write global bit line and the read global bit line suppress coupling noise generated during a read-while-write operation.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or more second resistance distributions, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit being adapted to supply compensation current to a sensing node, an amount of the compensation current varying based on the resistance of each reference cell, and the sense amplifier being adapted to compare the level of the sensing node with a reference level and to output a comparison result.

Abstract: According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example, the first crystalline phase may be a hexagonal closed packed structure, and the first crystalline phase may be a face centered cubic structure.

Abstract: A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.

Abstract: A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

Abstract: A write driver circuit for a memory that includes phase-change memory cells changeable between a RESET state resistance and a SET state resistance in response to an applied current pulse, the write driver circuit including a write current level adjusting unit configured to determine first to n-th SET state current levels in response to a SET state current level signal, where n is an integer greater than 1, and configured to determine a RESET state current level in response to a RESET state current level signal, and a write current output unit configured to generate one of a SET state current pulse and a RESET state current pulse corresponding to a SET state current level or a RESET state current level determined by the write current level adjusting unit.

Abstract: A phase random access memory including a plurality of access transistors, each access transistor including a drain region and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

Abstract: The nonvolatile memory device includes a plurality of memory banks, each of which includes a plurality of nonvolatile memory cells. Each cell includes a variable resistive element having a resistance varying depending on stored data. A plurality of global bit lines are included, and each global bit line is shared by the plurality of memory banks. A plurality of main word lines are arranged corresponding to one of the plurality of memory banks.

Abstract: A power supplying circuit (PSC) and a phase-change random access memory (PRAM) including the PSC. According to an aspect of the invention, the PSC includes: a first voltage generator configured to output a first voltage to a first terminal; and a second voltage generator configured to output a second voltage to a second terminal, the second voltage generator including: a voltage pump unit configured to output the second voltage based on a clock signal and a pump control signal; a pump output detector coupled to the voltage pump unit, the pump output detector configured to output a pump output detection signal; and a discharging unit coupled to the voltage pump unit, the discharging unit configured to discharge a level of the second voltage to a predetermined level in response to a discharge signal. Embodiments of the invention may prevent write and/or read malfunctions that can occur due to changes in the level of a voltage supplied to PRAM cell blocks.

Abstract: A phase change random access (PRAM) memory may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

Abstract: A nonvolatile memory device is configured to increase the reliability of a write operation by providing a sufficiently high write current while reducing current consumption in a read operation. The nonvolatile memory device includes a memory cell array having a plurality of nonvolatile memory cells. A global bit line and a local bit line coupled to a plurality of the nonvolatile memory cells. The local bit line has first and second nodes. First and second bit line selection circuits are included where the first bit line selection circuit is coupled to the first node of the local bit line and the second bit line selection circuit is coupled to the second node of the local bit line. The first and second bit line selection circuits operate during a first period to electrically connect the local bit line to the global bit line, and only one of the first and second bit line selection circuits operates during a second period to electrically connect the local bit line to the global bit line.

Abstract: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.

Abstract: A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

Abstract: A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.