Abstract: The present invention provides a semiconductor device and a manufacturing method capable of preventing penetration of plasma with impurities into an interface between an inter-layer insulation layer and a diffusion barrier, thereby reducing degradation of the capacitor properties and increasing production yield. The inventive semiconductor device, including: a capacitor formed on a top portion of a semiconductor substrate, wherein the capacitor includes a bottom electrode, a dielectric layer and a top electrode; an Iridium (Ir) capping layer formed on the top electrode of the capacitor; an inter-layer insulation layer for covering the capacitor and the Ir capping layer; a Ti layer for preventing plasma with impurities from penetrating into the capacitor through a contact hole, wherein the Ti layer is contacted with the inter-layer insulation layer exposed on lateral sides of the contact hole and the Ir capping layer exposed on a lower side of the contact hole; and a metal line formed on the Ti layer.

Abstract: A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure, formed on top of the first insulating layer and composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection, wherein the hydrogen barrier layer is made of an aluminum oxide (AlxOy) layer.

Abstract: A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure, formed on top of the first insulating layer and composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection, wherein the hydrogen barrier layer is made of an aluminum oxide (AlxOy) layer.

Abstract: The present invention provides a semiconductor device and a manufacturing method capable of preventing penetration of plasma with impurities into an interface between an inter-layer insulation layer and a diffusion barrier, thereby reducing degradation of the capacitor properties and increasing production yield. The inventive semiconductor device, including: a capacitor formed on a top portion of a semiconductor substrate, wherein the capacitor includes a bottom electrode, a dielectric layer and a top electrode; an Iridium (Ir) capping layer formed on the top electrode of the capacitor; an inter-layer insulation layer for covering the capacitor and the Ir capping layer; a Ti layer for preventing plasma with impurities from penetrating into the capacitor through a contact hole, wherein the Ti layer is contacted with the inter-layer insulation layer exposed on lateral sides of the contact hole and the Ir capping layer exposed on a lower side of the contact hole; and a metal line formed on the Ti layer.

Abstract: A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure, formed on top of the first insulating layer and composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection, wherein the hydrogen barrier layer is made of an aluminum oxide (AlxOy) layer.

Abstract: A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure formed on top of the first insulating layer, composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection.

Abstract: A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure, formed on top of the first insulating layer and composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection, wherein the hydrogen barrier layer is made of an aluminum oxide (AlxOy) layer.

Abstract: A method for manufacturing a ferroelectric memory device including steps of forming a ferroelectric layer, carrying out a rapid thermal process (RTP) to the ferroelectric layer to form perovskite crystal nuclei therein, and carrying out a heat treatment to the ferroelectric layer below 650° C. in the presence of O2 gas to crystallize the ferroelectric layer.

Abstract: The present invention discloses a ferroelectric memory device and a method for fabricating the same.

Abstract: A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure, formed on top of the first insulating layer, composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a hydrogen barrier layer, formed on the capacitor structure, for protecting the capacitor structure from hydrogen diffusion; a second insulating layer formed on top of the transistor and the capacitor structure; and a metal interconnection formed on top of the second insulating layer to electrically connect the transistor to the capacitor structure.

Abstract: A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure formed on top of the first insulating layer, composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection.