Abstract: A computer-implemented method of extracting parasitics associated with a circuit design layout generated by modifying a previous iteration of the layout, includes, in part, identifying a first multitude of nets that have been changed in the circuit design layout relative to the previous iteration of the circuit design layout. The method further includes, in part, calculating a first multitude of parasitic capacitance values between each of the first multitude of first nets and each of a second multitude of nets disposed in proximity of the first multitude of nets. The method further includes, in part, identifying each net in the second multitude of nets as an aggressor net if a number defined by the net's associated parasitic capacitance value is higher than a threshold value. The method further includes excluding nets in the second multitude of second nets that are not identified as aggressor nets from the parasitic extraction.

Abstract: A computer-implemented method of extracting parasitics associated with a circuit design layout generated by modifying a previous iteration of the layout, includes, in part, identifying a first multitude of nets that have been changed in the circuit design layout relative to the previous iteration of the circuit design layout. The method further includes, in part, calculating a first multitude of parasitic capacitance values between each of the first multitude of first nets and each of a second multitude of nets disposed in proximity of the first multitude of nets. The method further includes, in part, identifying each net in the second multitude of nets as an aggressor net if a number defined by the net's associated parasitic capacitance value is higher than a threshold value. The method further includes excluding nets in the second multitude of second nets that are not identified as aggressor nets from the parasitic extraction.

Abstract: One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file. The system then combines the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.

Abstract: One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file. The system then combines the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.

Abstract: One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which includes nominal parameter values for a first interconnect layer, and parameter-variation values which represent variations in the nominal parameter values due to random process variations. Next, the system receives an interconnect template which describes the geometry of a portion of a second interconnect layer. The system then determines electrical property data for the interconnect template using the interconnect technology data. The electrical property data can include a nominal electrical property value, and sensitivity values which represent the sensitivities of the nominal electrical property value to variations in the nominal parameter values. Next, the system stores the electrical property data and the interconnect technology data in a storage.

Abstract: One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which includes nominal parameter values for a first interconnect layer, and parameter-variation values which represent variations in the nominal parameter values due to random process variations. Next, the system receives an interconnect template which describes the geometry of a portion of a second interconnect layer. The system then determines electrical property data for the interconnect template using the interconnect technology data. The electrical property data can include a nominal electrical property value, and sensitivity values which represent the sensitivities of the nominal electrical property value to variations in the nominal parameter values. Next, the system stores the electrical property data and the interconnect technology data in a storage.