Abstract: Methods and systems for fast, low power PCM memory using a bitline precharge scheme in which unselected bitlines are driven to predetermined voltages and a selected bitline is set to ground, such that when selected and unselected bitlines are shorted together, the selected bitline is charged to a PCM sense voltage. Inventive methods and systems do not require a precharge voltage regulator to drive selected bitlines to a sense voltage.

Abstract: Systems and devices in which multi-bit phase change memory is used, including memory systems and memories, as well as methods for operating such systems and devices. According to the present invention, a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from multiple phase change memory reference cells designated to store said adjacent logical states. By writing reference cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track output changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. Ordering of states within said reference cells can be used to encode information such as checksums of corresponding words.

Abstract: Phase-change memory arrays, subarrays and chips, and systems and devices in which phase change memory is used, in which two reference columns are added on to hold complementary states for each wordline of data. The outputs from the cells in the two reference columns are combined (e.g. as a plain or weighted average) to provide a reference value for read discrimination of cell states in the other columns. This provides reference values which closely track resistance changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. One of the columns of reference cells can hold a checksum.

Abstract: Phase change memory arrays, subarrays, modules, and chips, as well as systems and devices in which phase change memory is used, wherein a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from a designated data-storing cell and a designated reference cell storing the logical complement to the logical state stored by the data-storing cell. By writing designated cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track resistance changes in said words resulting from, e.g., drift and other time- and phase change material-dependent factors.

Abstract: Phase change memory arrays, subarrays, modules, and chips, as well as systems and devices in which phase change memory is used, wherein a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from a designated data-storing cell and a designated reference cell storing the logical complement to the logical state stored by the data-storing cell. By writing designated cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track resistance changes in said words resulting from, e.g., drift and other time- and phase change material-dependent factors.

Abstract: Phase-change memory arrays, subarrays and chips, and systems and devices in which phase change memory is used, in which two reference columns are added on to hold complementary states for each wordline of data. The outputs from the cells in the two reference columns are combined (e.g. as a plain or weighted average) to provide a reference value for read discrimination of cell states in the other columns. This provides reference values which closely track resistance changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. One of the columns of reference cells can hold a checksum.

Abstract: Methods and systems for phase change memory having high RESET currents. In some sample embodiments, PCM elements share access devices in parallel between bit lines, permitting higher RESET currents to be shared between several access devices without overdriving. Lower individual current densities permit smaller access devices and smaller memories having greater reliability and longer retention. In some sample embodiments, hybrid arrays connect bit lines on only a few word lines, using the shared bits e.g. only for critical information. In some sample embodiments, several PCM elements share a single larger access device which can pass higher currents while still reducing the total memory size.

Abstract: A memory in which a comparison of PCM memory elements storing logical values to a trigger resistance or to each other can be used to determine the extent of resistance drift since the PCM memory elements were last written. If the comparison determines that the resistance drift has passed a sense margin threshold or a trigger resistance, a memory refresh is triggered and pre-drift resistances corresponding to the stored logical values are written to the PCM memory elements.

Abstract: Systems in which multi-bit PCM is used, including memory systems, as well as methods for operating such systems. A test of multi-bit PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read multi-bit PCM. This can be used to accelerate availability of memory states residing in multi-bit PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful.

Abstract: Systems in which PCM is used, including memory systems, as well as methods for operating such systems. A test of PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read PCM. This can be used to accelerate availability of memory states residing in PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful.

Abstract: The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data.

Abstract: Systems in which PCM is used, including memory systems, as well as methods for operating such systems. A comparison of PCM memory elements storing logical values to a trigger resistance or to each other can be used to determine the extent of resistance drift since the PCM memory elements were last written. If the comparison determines that the resistance drift has passed a sense margin threshold or a trigger resistance, a memory refresh is triggered and pre-drift resistances corresponding to the stored logical values are written to the PCM memory elements.

Abstract: Systems in which multi-bit PCM is used, including memory systems, as well as methods for operating such systems. A test of multi-bit PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read multi-bit PCM. This can be used to accelerate availability of memory states residing in multi-bit PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful.

Abstract: Methods and systems for phase change memory having high RESET currents. In some sample embodiments, PCM elements share access devices in parallel between bit lines, permitting higher RESET currents to be shared between several access devices without overdriving. Lower individual current densities permit smaller access devices and smaller memories having greater reliability and longer retention. In some sample embodiments, hybrid arrays connect bit lines on only a few word lines, using the shared bits e.g. only for critical information. In some sample embodiments, several PCM elements share a single larger access device which can pass higher currents while still reducing the total memory size.