Abstract: A data transmission link including a transmitter for acquiring conducted electrical data and transmitting electromagnetic radiated wave data such as optical data corresponding to the conducted electrical data, a receiver for receiving the electromagnetic radiated wave data and generating conducted electrical data corresponding to the radiated wave data and at least one wave conduit such as fiber optic data transmission cable for transmitting the radiated wave data from the transmitter to the receiver is disclosed. In one arrangement, the transmitter includes a light emitting device which is driven by an output driver responsive to the electrical data accepted by an input gate.

Abstract: A differential stage of an amplifier includes an input transistor and a second transistor with a significantly greater emitter cross-sectional area than the input transistor. Quiescent emitter current is divided between the two transistors in substantially the same ratio as the emitter cross-sectional areas so that the emitter current densities are substantially equal.

Abstract: A method and apparatus for altering the apparent electrical characteristic of a distributed electrical component in an integrated circuit is disclosed. In one form a distributed load resistor is sunk into a parallel distributed guard resistor. The mutual distributed capacitance between the distributed load resistor and the parallel distributed guard resistor is substantially greater than the distributed capacitance between the distributed load resistor and any other electrical component. A follower circuit for driving the voltage across the parallel distributed guard resistor by the voltage across the distributed load resistor is provided.

Abstract: The invention comprises a charge-coupled device shift register for storing and transferring bits of information in the form of small packets of charge. The apparatus utilizes multiphase clocking to allow for high density storage within the register which is comprised of three sections: serial input section, central storage section and serial output section. The serial input section receives charge packets synchronously from an injector circuit and is driven by two phase clocking. The central section forms the heart of the storage and transfer mechanism and is driven by multiphase clocking. The serial output section, also driven by two-phase clocking, synchronously emits charge packets which are sensed and amplified by a sense amplifier circuit.The input and output sections each contain (almost) twice the number of cell sites as the number of bits which are transferred in parallel through the central section. However, these sections store data bits in only every other cell site.

Abstract: A serial addressing system for arrays. Each array is comprised of a plurality of charge coupled device (CCD) registers. All of the registers comprising an array are addressed simultaneously, but only one of n arrays is accessed at a time. A serial address forming a stream of up to n bits containing only one 1 bit is propagated through address circuits for n array. The final position of the 1-bit determines which of the n arrays is accessed. Only the address circuits for properly functioning arrays form the bits of an n-bit address shift register, whereas the address circuits for improperly functioning arrays are shorted such that they do not form bits of the n-bit address shift register.

Abstract: The invention comprises circuitry for detecting relatively small amounts of charge emitted from a CCD register. The circuit acts as a differential amplifier, differentiating between charge levels corresponding to logical zeros and logical ones and generates corresponding system level logic signals. A reference charge is developed by a self-tracking reference charge injector. Both the reference charge and the charge packet to be sensed are coupled to the differential amplifier via buffering diode-coupled transistors. The circuit provides for a REFRESH mode of operation, but may be modified to also allow for READ, WRITE or PARTIAL-WRITE modes of operation.

Abstract: The invention comprises a charge-coupled device shift register for storing and transferring bits of information in the form of small packets of charge. The apparatus utilizes multiphase clocking to allow for high density storage within the register which is comprised of three sections: serial input section, central storage section and serial output section. The serial input section receives charge packets synchronously from an injector circuit and is driven by two-phase clocking. The central section forms the heart of the storage and transfer mechanism and is driven by multiphase clocking. The serial output section, also driven by two-phase clocking, synchronously emits charge packets which are sensed and amplified by a sense amplifier circuit. The input and output sections each contain the same number of cell sites as the number of bits which are transferred in parallel through the central section. However, these sections store data bits in only every other cell site.

Abstract: Interface circuitry for a charged coupled device (CCD) register system. The circuitry enables a PARTIAL-WRITE mode of operation on a CCD storage register. A data bus, which may be bi-directional, is coupled to the sense amplifier of the CCD storage register. The coupling is via interface circuitry responsive to control signals for enabling the register and also enabling a WRITE operation. Discontinuation of the WRITE signals frees the data bus for other uses, thereby allowing for a PARTIAL-WRITE mode of operation. The interface circuitry is simplified so as to require a minimum of space, thereby enhancing the density characteristics of the CCD storage system.

Abstract: The invention comprises a CCD memory chip. A CCD chip is comprised of a plurality of arrays, each of which is in turn comprised of a plurality of CCD registers. A serial addressing system may be used to determine which of the arrays is accessed. Fault-tolerance with respect to defective arrays is achieved by the combination of having only the address circuits for properly functioning arrays form the bits of an N-bit addressing shift register, (whereas the address circuits for improperly functioning arrays are shorted such that they do not form a bit of the N-bit address shift register,) and disabling the voltage delivered to a faulty array. The control circuitry includes the address circuitry and further includes means for controllably providing power to the array components. A plurality of arrays comprises a chip having pads for connecting the chip to the rest of the system.