Abstract: A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.

Abstract: A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.

Abstract: A chip is provided having processing circuits, each processing circuit configured to process a data vector to be stored according to a multiplication of the vector by a processing matrix, the sum of the processing matrices corresponding to the non-unit-matrix part of a generator matrix of a predetermined linear code in reduced form, a summing circuit to sum the results of the processing operations of the data vector, a storage circuit to store the data vector to be stored together with the sum of the generated results as one data word in a memory, a read-out circuit to read the stored data word out of the memory, and a decoding circuit to check whether the data word read out is a valid code word of the linear code and to output an error signal if the data word is not a valid code word of the linear code.

Abstract: A data processing device may have an instruction memory which is configured to store a computer program, a processing unit which is configured to execute the computer program, a program counter which is configured to specify a command of the computer program in the instruction memory as the next to be executed, a call stack, an encryption device which is configured to encrypt, when a subroutine is called in the computer program, a return address which specifies a command of the computer program in the instruction memory with which operations are to continue after the execution of the subroutine, and to store the encrypted return address in the call stack and a decryption device which is configured to read, after the execution of the subroutine, the encrypted return address from the call stack, to decrypt it and to set the program counter on the basis of the decrypted return address.

Abstract: A chip is provided having processing circuits, each processing circuit configured to process a data vector to be stored according to a multiplication of the vector by a processing matrix, the sum of the processing matrices corresponding to the non-unit-matrix part of a generator matrix of a predetermined linear code in reduced form, a summing circuit to sum the results of the processing operations of the data vector, a storage circuit to store the data vector to be stored together with the sum of the generated results as one data word in a memory, a read-out circuit to read the stored data word out of the memory, and a decoding circuit to check whether the data word read out is a valid code word of the linear code and to output an error signal if the data word is not a valid code word of the linear code.