Abstract: A method and apparatus for testing an electrically programmable read-only-memory which is embedded within logic or other digital circuitry on an integrated circuit is described. An integrated circuit tester is used to test the electrically programmable read-only-memory along with the logic or other digital circuitry by encoding certain test channels of the integrated circuit tester, and inputting the encoded test channels into a high voltage signal decoding circuit specially adapted to generating a high voltage, programming voltage required by the electrically programmable read-only-memory when the programming of certain test bits in the electrically programmable read-only-memory is conducted.

Abstract: A method for simulating a logic device is described wherein a sequence of input vectors to a computer simulation is reduced in order to save computational time and data storage requirements when the sequence includes a series of redundant input vectors having the same expected output vectors. The method reduces the number of redundant input vectors to be applied to the computer simulation by eliminating all but the first input vector of series while encoding a plurality of control bits associated with that input vector with information indicating the number of redundant input vectors being eliminated. Subsequently, after the simulation of the logic device, the output vectors resulting from the simulation are combined with their respective input vectors to form a set of test vectors.