Abstract: Sum bit generation circuit includes first logic generating first signal as XOR of first and second input signals and second signal as the inverse of XOR of the first and second input signals; second logic receiving the first and second signals generated by first logic and generating an output signal as XOR of first signal and third input signal. Second logic includes at least two pass gates. First gate terminal of the first pass gate receives third input signal. A second gate terminal of the first pass gate receives the inverse of third input signal. First gate terminal of the second pass gate receives the inverse of the third input signal. Second gate terminal of the second pass gate receives the third input signal. Input terminals of the first and second pass gates receive the first signal and the second signal respectively. Pass gate output terminals generate the output signal.

Abstract: Circuit for selecting a second set of binary inputs according to the number of high input signals applied to a first input set. A first subcircuit has the first input set, logic generating control output signals, each control output signal represents whether the first input set has exactly a predetermined number of high input signals. Each control output signal corresponds to a different predetermined number of high input signals. A second subcircuit has a second input set, a set of control inputs for receiving control output signals from the first subcircuit, and logic including a plurality of switches including one or more pass gates. Each switching component switches to connect or isolate one of the second input set to a common output. The control inputs control the switches. The first and second subcircuits are configured such that only one switch can be switched to connect at a time.

Abstract: Sum bit generation circuit includes first logic generating first signal as XOR of first and second input signals and second signal as the inverse of XOR of the first and second input signals; second logic receiving the first and second signals generated by first logic and generating an output signal as XOR of first signal and third input signal. Second logic includes at least two pass gates. First gate terminal of the first pass gate receives third input signal. A second gate terminal of the first pass gate receives the inverse of third input signal. First gate terminal of the second pass gate receives the inverse of the third input signal. Second gate terminal of the second pass gate receives the third input signal. Input terminals of the first and second pass gates receive the first signal and the second signal respectively. Pass gate output terminals generate the output signal.

Abstract: Circuit for selecting a second set of binary inputs according to the number of high input signals applied to a first input set. A first subcircuit has the first input set, logic generating control output signals, each control output signal represents whether the first input set has exactly a predetermined number of high input signals. Each control output signal corresponds to a different predetermined number of high input signals. A second subcircuit has a second input set, a set of control inputs for receiving control output signals from the first subcircuit, and logic including a plurality of switches including one or more pass gates. Each switching component switches to connect or isolate one of the second input set to a common output. The control inputs control the switches. The first and second subcircuits are configured such that only one switch can be switched to connect at a time.