Abstract: Embodiments are disclosed for managing multiple data visualizations on a digital canvas. In some embodiments, a method of managing multiple data visualizations includes generating a first graphic object on a digital canvas. A first dataset is received and used to generate a first chart based on the first dataset and a visual property of the first graphic object. The first chart comprises a first plurality of graphic objects including the first graphic object. A second dataset is then received and used to generate a second chart on the digital canvas based on the second dataset. The second chart includes a second plurality of graphic objects. An axis of the first chart and an axis of the second chart are merged such that the axis the first chart and the axis of the second chart share a scale attribute.

Abstract: Embodiments are disclosed for binding colors to data visualizations on a digital canvas. In some embodiments, a method of binding colors to data visualizations includes receiving a data set including data associated with a variable. A chart, including a plurality of graphic objects, is generated based on the variable of the data set and a visual property of the plurality of graphic objects. A data type associated with the variable determined and first colors are assigned to the plurality of graphic objects based on the data type using a color binding. A selection of second colors to be assigned to the plurality of graphic objects is received and the chart is updated using the second colors.

Abstract: Embodiments are disclosed for generating a data visualization. In some embodiments, a method of generating a data visualization includes generating a first graphic object on a digital canvas. A data set including data associated with a plurality of variables is added to a data panel of the digital canvas. A selection of a variable from the plurality of variables on the data panel is received and a second graphic object connecting the variable and a cursor position on the digital canvas is generated. A selection of a visual property of the first graphic object is received using the cursor. Upon selection of the visual property, the first graphic object is linked to the data panel via the second graphic object. A chart is then generated comprising the first graphic object and one or more new graphic objects, based on the variable and the visual property of the first graphic object.

Abstract: A system for serial communication includes a controller, a semiconductor package comprising a plurality of semiconductor die, and a serial interface configured to connect the plurality of semiconductor die to the controller. The serial interface includes a controller-to-package connection and a package-to-controller connection, and the serial interface is configured to employ a signaling protocol using differential data signaling with no separate clock signals.

Abstract: A system for serial communication includes a controller, a semiconductor package comprising a plurality of semiconductor die, and a serial interface configured to connect the plurality of semiconductor die to the controller. The serial interface includes a controller-to-package connection and a package-to-controller connection, and the serial interface is configured to employ a signaling protocol using differential data signaling with no separate clock signals.

Abstract: A packaging for transporting and/or storing radioactive materials, the lateral body of which has a thickness change zone defining a transition surface, and including a portion of reduced thickness extending from the transition surface towards a first axial end of the lateral body, this portion of reduced thickness including an inner surface laterally delimiting a recessed zone of the lateral body, also delimited axially by the transition surface. Moreover, the packaging includes a portion reconstituting the lateral body extending around the longitudinal axis, arranged removably in the recessed zone, and having an inner surface that laterally delimits a portion of the housing cavity intended to receive the mass of radioactive materials.

Abstract: An aircraft braking system for an aircraft, the aircraft including first and second brakes, and first and second energy distribution systems for delivering energy to the first and second brakes to operate the respective first and second brakes. The aircraft braking system is switchable between: a first configuration, in which the first energy distribution system is coupled to the first brake and is isolated from the second brake, and the second energy distribution system is coupled to the second brake and is isolated from the first brake; and a second configuration, in which the first energy distribution system is coupled to both the first and second brakes.

Abstract: A semiconductor chip includes a semiconductor die formed on a substrate, a first power mesh formed on the substrate, and a second power mesh formed on the substrate electrically isolated from the first power mesh. The semiconductor chip also includes a first circuit block formed on the substrate and electrically connected to the first power mesh, and a second circuit block formed on the substrate and electrically connected to the second power mesh. The first circuit block and the second circuit block are communicatively coupled to a first plurality of external circuit connections and a second plurality of external circuit connections, respectively. The semiconductor chip also includes one or more first signal pins and one or more second signal pins formed on the substrate, the first and second signal pins designed to receive external signals.

Abstract: A packaging for transporting and/or storing radioactive materials, the lateral body of which has a thickness change zone defining a transition surface, and including a portion of reduced thickness extending from the transition surface towards a first axial end of the lateral body, this portion of reduced thickness including an inner surface laterally delimiting a recessed zone of the lateral body, also delimited axially by the transition surface. Moreover, the packaging includes a portion reconstituting the lateral body extending around the longitudinal axis, arranged removably in the recessed zone, and having an inner surface that laterally delimits a portion of the housing cavity intended to receive the mass of radioactive materials.

Abstract: A semiconductor chip includes a semiconductor die formed on a substrate, a first power mesh formed on the substrate, and a second power mesh formed on the substrate electrically isolated from the first power mesh. The semiconductor chip also includes a first circuit block formed on the substrate and electrically connected to the first power mesh, and a second circuit block formed on the substrate and electrically connected to the second power mesh. The first circuit block and the second circuit block are communicatively coupled to a first plurality of external circuit connections and a second plurality of external circuit connections, respectively. The semiconductor chip also includes one or more first signal pins and one or more second signal pins formed on the substrate, the first and second signal pins designed to receive external signals.

Abstract: A semiconductor chip includes a semiconductor die formed on a substrate, a first power mesh formed on the substrate, and a second power mesh formed on the substrate electrically isolated from the first power mesh. The semiconductor chip also includes a first circuit block formed on the substrate and electrically connected to the first power mesh, and a second circuit block formed on the substrate and electrically connected to the second power mesh. The first circuit block and the second circuit block are communicatively coupled to a first plurality of external circuit connections and a second plurality of external circuit connections, respectively. The semiconductor chip also includes one or more first signal pins and one or more second signal pins formed on the substrate, the first and second signal pins designed to receive external signals.

Abstract: A semiconductor chip includes a semiconductor die formed on a substrate, a first power mesh formed on the substrate, and a second power mesh formed on the substrate electrically isolated from the first power mesh. The semiconductor chip also includes a first circuit block formed on the substrate and electrically connected to the first power mesh, and a second circuit block formed on the substrate and electrically connected to the second power mesh. The first circuit block and the second circuit block are communicatively coupled to a first plurality of external circuit connections and a second plurality of external circuit connections, respectively. The semiconductor chip also includes one or more first signal pins and one or more second signal pins formed on the substrate, the first and second signal pins designed to receive external signals.

Abstract: A method for validating the design of an electronic circuit uses a static checker tool to verify the circuit design against rules and attributes of the components of the circuit. A power intent of the circuit, pins for power, ground and data signal inputs and outputs for each component, and a model for attributes and parameters of the pins are defined. The attributes of the components are defined in terms of input and output voltages; input and output currents; input and output voltage, current and data signal timing; and input and output voltage and current ranges and tolerances. A netlist of interconnections representing the designed circuit is validated against the power intent and the model for the attributes. A report is output describing the validity of the circuit based on the compatibility of the netlist, the power intent, and the model for the attributes of the components.

Abstract: A method for validating the design of an electronic circuit uses a static checker tool to verify the circuit design against rules and attributes of the components of the circuit. A power intent of the circuit, pins for power, ground and data signal inputs and outputs for each component, and a model for attributes and parameters of the pins are defined. The attributes of the components are defined in terms of input and output voltages; input and output currents; input and output voltage, current and data signal timing; and input and output voltage and current ranges and tolerances. A netlist of interconnections representing the designed circuit is validated against the power intent and the model for the attributes. A report is output describing the validity of the circuit based on the compatibility of the netlist, the power intent, and the model for the attributes of the components.

Abstract: Embodiments of methods, apparatuses, and systems to transport Time Division Multiplexed (TDM) utilizing symbol encoded physical layer are disclosed. The embodiments of the invention provide a low cost solution to exchange data between TDM data elements while retaining guaranteed performance. A media access control layer generates framed data and the system guarantees delivery of the framed data to the designated destination within a fixed interval period of time.

Abstract: There is disclosed a telephony apparatus comprising a base station and a handset, one of the base station and the handset being connected to a telephony system via an IEEE 802.11 interface, the base station and the handset each further being provided with an Bluetooth interface, speech data and/or control data being transmitted between the base station and the handset on said Bluetooth interface.

Abstract: The device detects the beginning and ending portions of speech contained within an input signal based on the variance of smoothed frequency band limited energy and the history of the smoothed frequency band limited energy within the signal. The use of the variance allows detection which is relatively independent of an absolute signal-to-noise ratio with the signal, and allows accurate detection within a wide variety of backgrounds such as music, motor noise, and background noise, such as other voices. The device can be easily implemented using off-the-shelf hardware along with a high-speed special purpose digital signal processor integrated circuit.