Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.

Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.

Abstract: A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.

Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells and a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank. The memory also comprises a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, and wherein a write verification operation associated with a data word of the second plurality of data words is performed a predetermined period of time after the data word is written into the memory.

Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.

Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Also, the cache memory is divided into a plurality of segments, wherein each segment of the cache memory is direct mapped to a corresponding segment of the memory bank, wherein an address of each of the second plurality of data words is mapped to a corresponding segment in the cache memory, and wherein data words from a particular segment of the memory bank only get stored in a corresponding direct mapped segment of the cache memory.

Abstract: A method of writing data utilizes a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method also comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification. Additionally, the method comprises searching for at least one data word that is awaiting write verification in the error buffer, wherein verify operations associated with the at least one data word occur in a same row as the write operation. Finally, the method comprises determining if an address associated with any of the at least one data word is proximal to an address for the write operation and preventing a verify operation associated with the at least one data word from occurring in a same cycle as the write operation.

Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank and writing a second plurality of data words and associated memory addresses into an error buffer. The method also comprises monitoring a first counter value which tracks a number of write 1 errors and a second counter value which tracks a number of write 0 errors in the memory bank. Further, the method comprises determining if the first counter value and the second counter value have exceeded a predetermined threshold. Responsive to a determination that the first counter value has exceeded the predetermined threshold increasing a write 1 voltage of the memory bank, and, further, responsive to a determination that the second counter value has exceeded the predetermined threshold increasing a write 0 voltage of the memory bank.

Abstract: A method of writing data into a memory device discloses utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification associated with the memory bank. The method further comprises searching for a data word that is awaiting write verification in the error buffer, wherein the verify operation occurs in a same row as the write operation. The method also comprises determining if an address of the data word is proximal to an address for the write operation and responsive to a positive determination, delaying a start of the verify operation so that a rising edge of the verify operation occurs a predetermined delay after a rising edge of the write operation.

Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells and a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank. The memory also comprises a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, and wherein a write verification operation associated with a data word of the second plurality of data words is performed a predetermined period of time after the data word is written into the memory.

Abstract: A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.

Abstract: An memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A first circuit provides a first voltage on an addressed bit line of the plurality of bit lines during a write cycle, wherein the addressed bit line corresponds to an addressed memory cell.

Abstract: A memory device comprises a memory bank comprising a plurality of memory addresses. The memory device further comprises a first level dynamic redundancy register comprising data storage elements and a pipeline bank coupled to the memory bank and the first level dynamic redundancy register, wherein the pipeline bank is configured to: (a) write a data word into the memory bank at a selected one of the plurality of memory addresses; (b) verify the data word written into the memory bank to determine whether the data word was successfully written by the write; and (c) responsive to a determination that the data word was not successfully written by the write, writing the data word into the first level dynamic redundancy register, wherein the memory bank is fabricated on a first die and further wherein the first level dynamic redundancy register is fabricated on a second die.

Abstract: A clocked driver circuit can include a master-slave level shifter latch and a driver. The master-slave level shifter latch can be configured to receive an input signal upon a first state of a clock signal, latch the input signal upon a second state of the clock signal and generate a level shifted output signal corresponding to the latched input signal. The driver can be configured to receive the level shifted output signal from the master-slave level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.

Abstract: A clocked driver circuit can include a master-slave level shifter latch and a driver. The master-slave level shifter latch can be configured to receive an input signal upon a first state of a clock signal, latch the input signal upon a second state of the clock signal and generate a level shifted output signal corresponding to the latched input signal. The driver can be configured to receive the level shifted output signal from the master-slave level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.

Abstract: A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.

Abstract: A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.

Abstract: A method for correcting bit defects in an STT-MRAM memory is disclosed. The method includes reading a codeword in the STT-MRAM memory, wherein the STT-MRAM memory includes a plurality of codewords, wherein each codeword includes a plurality of redundant bits. Further, the method includes mapping defective bits in the codeword to redundant bits of the plurality of redundant bits based on a mapping scheme, wherein the mapping scheme is operable to determine a manner in which the defective bits in the codeword are to be mapped to the redundant bits. Finally, the method includes replacing the defective bits in the codeword with corresponding mapped redundant bits.

Abstract: A memory device for storing data is disclosed. The memory device comprises a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells. The memory device also comprises a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks. Further, the device comprises a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.

Abstract: A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.