Patents by Inventor Benjamin M. Cahill, III

Benjamin M. Cahill, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5812217
    Abstract: A method and apparatus for the self-correcting of anti-ghosting filter coefficients is provided. A plurality of coefficients associated with an anti-ghosting filter are monitored as data is received by the filter. The plurality of coefficients are adjusted if one or more of the plurality of coefficients exceed a first value. In one embodiment, the filter is an adaptive baseband equalization filter. If the magnitude of one or more secondary coefficients of the adaptive baseband equalization filter exceed a predetermined factor of the primary coefficient, then the plurality of coefficients are adjusted. In another embodiment, the filter is a lookup table filter. If the magnitude of a coefficient in the lookup table is greater than a predetermined value, the plurality of coefficients are adjusted.
    Type: Grant
    Filed: June 26, 1996
    Date of Patent: September 22, 1998
    Assignee: Intel Corporation
    Inventor: Benjamin M. Cahill, III
  • Patent number: 5812207
    Abstract: A method and apparatus for supporting variable oversampling ratios when decoding vertical blanking interval data receives an indication of an oversampling ratio being used to sample a signal received during the vertical blanking interval. The sampled signal is also received. Then, based on the indication of the oversampling ratio being used, the data embedded in the vertical blanking interval is identified.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: September 22, 1998
    Assignee: Intel Corporation
    Inventor: Benjamin M. Cahill, III
  • Patent number: 5784047
    Abstract: A display scaler of the present invention typically includes (a) a memory for sending data, (b) a first variable length buffer for receiving the data from the memory, (c) a first scaler for scaling the data in a first direction, (d) a buffer controller for controlling the first buffer, (e) a memory controller for controlling sending of the data from the memory to the first variable length buffer, and (f) a main display controller for sending control signals to the first scaler, the buffer controller, and the memory controller. The display scaler may further include (g) a second buffer for receiving the scaled data from the first scaler and (h) a second scaler for scaling the scaled data in a second direction. The present invention provides a method of generating a first image on a first display window and a second image on a second display window.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: July 21, 1998
    Assignee: Intel Corporation
    Inventors: Benjamin M. Cahill, III, Anthony Paul Bertapelli, Tim N. Hanna
  • Patent number: 5784046
    Abstract: A plurality of image signals corresponding to a row of an image are selected based on digital differential accumulator processing. A plurality of weighted image signals are generated by multiplying the plurality of image signals by one or more weight factors selected in accordance with the digital differential accumulator processing. A weighted sum signal is generated by summing the plurality of weighted image signals and a horizontally scaled image signal is generated corresponding to the plurality of image signals from the weighted sum signal.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: July 21, 1998
    Assignee: Intel Corporation
    Inventor: Benjamin M. Cahill, III
  • Patent number: 5754162
    Abstract: An odd pixel and an even pixel of a row of an image are selected in accordance with digital differential accumulator processing. An odd-pixel weight factor and an even-pixel weight factor are selected in accordance with the digital differential accumulator processing. A weighted odd-pixel image signal is generated by multiplying an image signal corresponding to the odd pixel by the odd-pixel weight factor and a weighted even-pixel image signal is generated by multiplying an image signal corresponding to the even pixel by the even-pixel weight factor. A horizontally scaled image signal is generated by adding the weighted odd-pixel signal and the weighted even-pixel image signal.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: May 19, 1998
    Assignee: Intel Corporation
    Inventor: Benjamin M. Cahill, III
  • Patent number: 5717436
    Abstract: The single image support component comprises (a) a capture interface for capture scaling image signals; (b) a host interface for transmitting compressed image signals to a host processor and for receiving compressed image signals from the host processor; (c) a pixel processor interface for transmitting uncompressed image signals to and receiving compressed image signals from a pixel processor and for transmitting compressed image signals to and receiving decompressed image signals from the pixel processor; (d) a memory interface for storing and accessing the capture scaled image signals as a capture scaled bitmap in a memory device, for storing and accessing the compressed image signals as a compressed bit stream in the memory device, and for storing and accessing the decompressed image signals as a decompressed bitmap in the memory device; and (e) a display interface for display scaling one of the capture scaled image signals and the decompressed image signals.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: February 10, 1998
    Assignee: Intel Corporation
    Inventor: Benjamin M. Cahill, III
  • Patent number: 5694148
    Abstract: A current row and a next row of an image are selected in accordance with digital differential accumulator processing. A current-row weight factor and a next-row weight factor are selected in accordance with the digital differential accumulator processing. Weighted current-row image signals are generated by multiplying a plurality of image signals of the current row by the current-row weight factor and weighted next-row image signals are generated by multiplying a plurality of image signals of the next row by the next-row weight factor. Vertically scaled image signals are generated by adding the weighted current-row image signals and the weighted next-row image signals.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: December 2, 1997
    Assignee: Intel Corporation
    Inventor: Benjamin M. Cahill, III
  • Patent number: 5694149
    Abstract: A plurality of image signals corresponding to a first portion of a first row of an image are received. A plurality of first-row weighted image signals are generated by multiplying each of the plurality of first-row image signals by a first-row weight factor selected in accordance with digital differential accumulator processing. A plurality of image signals corresponding to a first portion of a second row of the image are received. A plurality of second-row weighted image signals are generated by multiplying each of the plurality of second-row image signals by a second-row weight factor selected in accordance with the digital differential accumulator processing. A plurality of weighted sum signals are generated by adding the plurality of first-row weighted image signals and the plurality of second-row weighted image signals. A plurality of vertically scaled image signals are generated from the weighted sum signals.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: December 2, 1997
    Assignee: Intel Corporation
    Inventor: Benjamin M. Cahill, III
  • Patent number: 5682179
    Abstract: A plurality of image signals corresponding to an image are received. One or more first-sum signals are generated by adding together one or more pairs of image signals and one or more second-sum signals are generated by adding together one or more pairs of the first-sum signals. One or more first-average signals are generated in accordance with the first-sum signals and one or more second-average signals are generated in accordance with the second-sum signals. The image signals, the first-average signals, and the second-average signals are selectively stored into a plurality of registers in accordance with the selection of a mode of operation of a plurality of modes of operation.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: October 28, 1997
    Assignee: Intel Corporation
    Inventor: Benjamin M. Cahill, III
  • Patent number: 5668594
    Abstract: A method and apparatus for raster calibration is described. Calibration circuitry operates in the context of a local video subsystem which receives at least one sync signal from a remote video (typically graphics) subsystem. The calibration circuitry calibrates a local raster of the local video subsystem to a remote raster of the remote video subsystem. The calibration circuitry includes measurement circuitry for measuring a first duration of a first phase of the sync signal, and for measuring a second duration of a second phase of the sync signal. Processing logic compares the first and second durations and determines that the phase having the shorter duration is an active phase, the active phase corresponding to the polarity of the sync signal. The processing logic also adds the first and second durations to provide an estimate of the scan line period of the remote raster.
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: September 16, 1997
    Assignee: Intel Corporation
    Inventor: Benjamin M. Cahill, III
  • Patent number: 5629719
    Abstract: Horizontal counter signals are generated and compared to a window left limit and a window right limit. Horizontal comparison signals are generated in accordance with that comparison. The horizontal counter signals are also compared to a horizontal limit and horizontal reset signals are generated in accordance with that comparison. Vertical counter signals are generated in accordance with the horizontal reset signals and compared to a window top limit and a window bottom limit. Vertical comparison signals are generated in accordance with that comparison. The vertical counter signals are also compared to a vertical limit and vertical reset signals are generated in accordance with that comparison. Image signals are displayed on a display monitor in accordance with the horizontal comparison signals and the vertical comparison signals.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: May 13, 1997
    Assignee: Intel Corporation
    Inventor: Benjamin M. Cahill, III
  • Patent number: 5619226
    Abstract: Image signals corresponding to a first row of the image are horizontally scaled and stored in an external memory device. A first portion of the horizontally scaled first-row image signals are retrieved from the external memory device and stored in an internal memory device. Image signals corresponding to a first portion of a second row of the image are horizontally scaled and partially vertically scaled first-portion image signals are generated from the first portion of the horizontally scaled first-row image signals and the first portion of the horizontally scaled second-row image signals. The partially vertically scaled first-portion image signals are stored in the external memory device. A second portion of the horizontally scaled first-row image signals are retrieved from the external memory device and stored in the internal memory device.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: April 8, 1997
    Assignee: Intel Corporation
    Inventor: Benjamin M. Cahill, III
  • Patent number: 5583536
    Abstract: Monochrome and color video mixers mix an overlay image with a default image to form a composite image to be displayed on a computer display. The monochrome video mixer includes a summing circuit for summing an overlay signal and a default signal to generate a composite signal. The overlay signal corresponds to the overlay image, the default signal corresponds to the default image, and the composite signal corresponds to the composite image. The video mixer includes a comparator that has a first input for receiving the composite signal and a second input for receiving the overlay signal. The comparator compares the signal level measured at the first input with the signal level measured at the second input. In response to the comparison, the comparator provides an enable signal in the presence of a default key color signal. In response to the enable signal, an enabling circuit in the video mixer provides the overlay signal to the summing circuit.
    Type: Grant
    Filed: June 9, 1994
    Date of Patent: December 10, 1996
    Assignee: Intel Corporation
    Inventor: Benjamin M. Cahill, III
  • Patent number: 4792981
    Abstract: A method and apparatus for manipulating run-length encoded rasterized images. Sizing, slanting, rotating or otherwise transforming an image outline to a new orientation is accomplished without converting image information into a bit map or discrete pixel format. An image outline is characterized in terms of visible and invisible vectors along an input raster scan line by relating run-lengths in a previous input scan line with run-lengths in a current input scan line. The resulting vector characterization allows determination of crossover points on output raster scan lines for the manipulated image by means of transform coefficients. Memory bins store these crossover points, and these bins are sorted to construct a new run-length encoded image outline.
    Type: Grant
    Filed: September 21, 1987
    Date of Patent: December 20, 1988
    Assignee: AM International, Inc.
    Inventors: Benjamin M. Cahill, III, Jeffrey R. Hedden