Abstract: A data storage device includes multiple flash memory devices, where each of the flash memory devices is arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices. The memory controller is configured to receive a logical to physical address translation map from a host device, where a physical address includes a physical address for one of the flash memory devices. The memory controller is configured to store the logical to physical address translation map in a memory module on the memory controller, receive read commands directly from an application running on the host device, where the read commands include logical memory addresses that refer to the logical locations on the flash memory devices, and translate the logical addresses to physical memory addresses using the logical to physical address translation map.

Abstract: A data storage device includes multiple flash memory devices, where each of the flash memory devices are arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller that is operationally coupled with the flash memory devices. The memory controller is configured to receive a virtual to physical memory address translation map from a host device, where a physical memory address includes a physical address for memory on the host device. The memory controller is configured to store the virtual to physical memory address translation map in a memory module on the memory controller, receive commands directly from an application running on the host device, where the commands include virtual memory addresses that refer to the memory on the host device and translate the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map.

Abstract: A data storage device includes multiple flash memory devices, where each of the flash memory devices is arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices. The memory controller is configured to receive a logical to physical address translation map from a host device, where a physical address includes a physical address for one of the flash memory devices. The memory controller is configured to store the logical to physical address translation map in a memory module on the memory controller, receive read commands directly from an application running on the host device, where the read commands include logical memory addresses that refer to the logical locations on the flash memory devices, and translate the logical addresses to physical memory addresses using the logical to physical address translation map.

Abstract: A data storage device includes multiple flash memory devices, where each of the flash memory devices are arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller that is operationally coupled with the flash memory devices. The memory controller is configured to receive a virtual to physical memory address translation map from a host device, where a physical memory address includes a physical address for memory on the host device. The memory controller is configured to store the virtual to physical memory address translation map in a memory module on the memory controller, receive commands directly from an application running on the host device, where the commands include virtual memory addresses that refer to the memory on the host device and translate the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map.

Abstract: An apparatus for error correction for a data storage device may include an input interface that is configured to receive individual error correction requests to correct data from multiple channel controllers and that is configured to receive error correction information corresponding to the error correction requests, where each of the channel controllers is arranged and configured to control operations associated with one or more memory chips. The apparatus may include a corrector module that is operably coupled to the input interface and that is arranged and configured to perform error correction using an error correction algorithm and the error correction information to generate correction solutions, where the corrector module is a shared resource for the multiple channel controllers. The apparatus may include an output interface that is operably coupled to the corrector module and that is arranged and configured to communicate the correction solutions to the channel controllers.

Abstract: An apparatus for error correction for a data storage device may include an input interface that is configured to receive individual error correction requests to correct data from multiple channel controllers and that is configured to receive error correction information corresponding to the error correction requests, where each of the channel controllers is arranged and configured to control operations associated with one or more memory chips. The apparatus may include a corrector module that is operably coupled to the input interface and that is arranged and configured to perform error correction using an error correction algorithm and the error correction information to generate correction solutions, where the corrector module is a shared resource for the multiple channel controllers. The apparatus may include an output interface that is operably coupled to the corrector module and that is arranged and configured to communicate the correction solutions to the channel controllers.