Patents by Inventor Benjamin Thomas Cope
Benjamin Thomas Cope has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220116678Abstract: In one embodiment, video content displayed across a plurality of display devices is synchronized by first obtaining a first set of VSYNC timestamps for a display controller of a first video display device and a second set of VSYNC timestamps for a display controller of a second video display device. An adjustment factor is determined based on a comparison of the first and second VSYNC timestamps, and an adjusted VSYNC period for the display controller of the second video display device is programmed based on the determined adjustment factor. After a predetermined number of VSYNC cycles, the display controller of the second video display device reverts back to an original VSYNC period.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Applicant: Intel CorporationInventors: Karthik Tyamgondlu, Benjamin Thomas Cope, Satyeshwar Singh, Sangeeta Ghangam Manepalli, Aswin Padmanabhan
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Patent number: 9485129Abstract: Integrated circuits with wireless communications circuitry having peak cancelation circuitry operable to perform crest factor reduction is provided. The peak cancelation circuitry may receive at least first and second carrier waveforms and may include at least a first canceling pulse generator (CPG), a second CPG, a first peak detector for performing peak detection on the first waveform, a second peak detector for performing peak detection on the second waveform, a third peak detector for performing peak detection on a combined waveform of the first and second waveforms, and a pulse allocator that receives clipping information from the three peak detectors and that controls the amount of peak cancelation that is being performed by the two CPGs. The allocator may determine whether the combined waveform contains any peaks. In response to determining that the combined waveform does not contain any peaks, the CPGs may be configured in bypass mode.Type: GrantFiled: July 7, 2014Date of Patent: November 1, 2016Assignee: Altera CorporationInventors: Benjamin Thomas Cope, Volker Mauer, Shahin Gheitanchi, Nima Safari
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Patent number: 9424210Abstract: Various structures and methods are disclosed related to efficiently accessing a memory for a particular application. An embodiment of the present invention utilizes characteristics of an access pattern for a particular application to provide a more efficient organization of data in a memory. In one embodiment, the predictability in access needs for a particular application is exploited to provide a data organization method for organizing data in an SDRAM memory to support efficient access. In one embodiment, the particular application is operation under the Long Term Evolution (“LTE”) standard for wireless communications. In one embodiment, associated hardware and methods are provided to, when necessary, reorder read commands and, when necessary, reorder data read from memory so that at least some of the time overhead for accessing one row can be hid behind an access of another row.Type: GrantFiled: October 22, 2010Date of Patent: August 23, 2016Assignee: Altera CorporationInventors: Benjamin Thomas Cope, Kulwinder Dhanoa, Lei Xu
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Patent number: 9077408Abstract: A method includes identifying a signal peak from an input signal. The signal peak may be detected with peak detection circuitry. A serial division operation may be performed on the identified signal peak value with serial division circuitry to obtain a scaling factor. The peak detection circuitry may identify an additional signal peak from the input signal concurrently with the serial division operation. The serial division operation may be halted if the additional identified signal peak is greater than the previous identified signal peak. Another serial division operation may be performed based on the additional identified signal peak.Type: GrantFiled: October 1, 2012Date of Patent: July 7, 2015Assignee: Altera CorporationInventors: Sharifuddin Sapuan Sahori, Benjamin Thomas Cope, Lei Xu
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Patent number: 9000802Abstract: Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.Type: GrantFiled: January 13, 2014Date of Patent: April 7, 2015Assignee: Altera CorporationInventors: Michael Fitton, Kulwinder Dhanoa, Benjamin Thomas Cope, Kellie Marks, Lei Xu
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Patent number: 8861304Abstract: Integrated circuits with wireless communications circuitry having peak cancelling circuitry operable to perform crest factor reduction is provided. The peak cancelling circuitry may include a peak detection circuit, a delay circuit, and peak cancellation pulse generation circuitry. The peak cancellation pulse generation circuitry may include multiple pulse generation blocks coupled in a cascade configuration. Each pulse generation block may include a counter for providing memory address signals, a register for latching peak scaling factor information, a pulse memory block for storing a respective sub-pulse, and a multiplier for scaling the stored sub-pulse by the latched peak scaling factor. The pulse memory block may be implemented using single-port memory or dual-port memory.Type: GrantFiled: September 24, 2012Date of Patent: October 14, 2014Assignee: Altera CorporationInventor: Benjamin Thomas Cope
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Patent number: 8825729Abstract: Systems and methods are disclosed for calculating Fast Fourier Transforms (FFT) in a power and memory bandwidth efficient manner. For example, an apparatus is provided that includes a memory interface operable to read data samples stored in a memory and store a first set of the data samples in a read reorder buffer, wherein the read reorder buffer selects a first portion of the first set of the data samples in accordance with a radix-reversed order. Also included is a first core circuit that is operable to process the first portion of the first set of the data samples in response to receiving the first portion from the read reorder buffer, wherein the processing includes calculating output samples corresponding to a part of an FFT.Type: GrantFiled: September 19, 2011Date of Patent: September 2, 2014Assignee: Altera CorporationInventors: Benjamin Thomas Cope, Martin Langhammer
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Publication number: 20140125379Abstract: Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.Type: ApplicationFiled: January 13, 2014Publication date: May 8, 2014Applicant: Altera CorporationInventors: Michael Fitton, Kulwinder Dhanoa, Benjamin Thomas Cope, Kellie Marks, Lei Xu
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Patent number: 8629691Abstract: Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.Type: GrantFiled: May 17, 2012Date of Patent: January 14, 2014Assignee: Altera CorporationInventors: Michael Fitton, Kulwinder Dhanoa, Benjamin Thomas Cope, Kellie Marks, Lei Xu
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Publication number: 20120319730Abstract: Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.Type: ApplicationFiled: May 17, 2012Publication date: December 20, 2012Applicant: ALTERA CORPORATIONInventors: Michael Fitton, Kulwinder Dhanoa, Benjamin Thomas Cope, Kellie Marks, Lei Xu