Abstract: A margin testing system comprises a margin testing controller and a frequency control module. The margin testing controller is internal to and integrated with an electronic system under test and is coupled with a plurality of components that are configured to provide the functionality of the electronic system under test. The plurality of components includes a processor of the electronic system under test. The frequency control module is in communication with the margin testing controller. The frequency control module is configured for varying a clock frequency associated with at least one of the components for frequency margin testing the at least one of the components in response to command of the margin testing controller.

Abstract: The present invention provides a margin testing system, incorporated in an electronic system (e.g., a computer system), that includes a controller, a frequency control module, and a voltage control module, and a fault bypass module. In response to commands from the controller, the frequency control module and/or the voltage control module can set a test clock frequency and/or a test voltage for application to one or more components of the electronic system to elicit system response to these test values. The response of the system at each test value can be monitored, e.g., by executing a diagnostics software, and analyzed. The fault bypass module can mask fault signals during margin testing to ensure that these signals will not disrupt margin testing of the system.

Abstract: The present invention provides systems and methods for performing frequency margin testing of a computer system, such as a server. A system of the invention can include a controller, e.g., a BMC, internal to the computer system and a digital frequency synthesizer that can communicate with the controller and can apply clock frequency to marginable components of the computer system. In response to commands from the controller, the synthesizer generates one or more test frequencies that are applied to one or more of the marginable components. The response of the system to each of the test frequencies is then monitored.

Abstract: The present invention provides a voltage margin testing system incorporated in an electronic system, such as, a computer system (e.g., a server), having a plurality of components for at least some of which voltage margin testing is required. A voltage margin testing of the invention can include a controller, such as a Baseboard Management Controller (BMC), internal to the computer system and a digital voltage adjuster, e.g., a digital potentiometer, that is in communication with the controller. The voltage adjuster can effect generation of one or more test voltages, for example, by varying resistance in a feedback circuitry of a regulator whose output voltage is applied to system components, for application to the components in response to commands from the controller.

Abstract: A computer data bus interface control selectively connects a computer data bus to functional components of a circuit board or isolates the bus from the functional components. The bus interface control also selectively provides pull-up voltage to the bus, as needed. The connection selection and the pull-up voltage selection can be made, for example, based on whether the board is installed in a system slot or a peripheral slot of the bus.

Abstract: The present invention provides a margin testing system, incorporated in an electronic system (e.g., a computer system), that includes a controller, a frequency control module, and a voltage control module, and a fault bypass module. In response to commands from the controller, the frequency control module and/or the voltage control module can set a test clock frequency and/or a test voltage for application to one or more components of the electronic system to elicit system response to these test values. The response of the system at each test value can be monitored, e.g., by executing a diagnostics software, and analyzed. The fault bypass module can mask fault signals during margin testing to ensure that these signals will not disrupt margin testing of the system.

Abstract: The present invention provides systems and methods for margin testing of one or more components of an electronic system, such as a computer system (e.g., a server). A margin testing system of the invention can include a fault bypass module incorporated in the electronic system for masking signals indicative of faults associated with one or more components during margin testing of the system. The margin testing system can also include a controller, such as a Baseboard Management Controller (BMC), internal to the electronic system that is in communication with the fault bypass module. The controller can transmit a command to the fault bypass module to initiate masking of selected faults by that module.

Abstract: The present invention provides a voltage margin testing system incorporated in an electronic system, such as, a computer system (e.g., a server), having a plurality of components for at least some of which voltage margin testing is required. A voltage margin testing of the invention can include a controller, such as a Baseboard Management Controller (BMC), internal to the computer system and a digital voltage adjuster, e.g., a digital potentiometer, that is in communication with the controller. The voltage adjuster can effect generation of one or more test voltages, for example, by varying resistance in a feedback circuitry of a regulator whose output voltage is applied to system components, for application to the components in response to commands from the controller.