Patents by Inventor Benjamin Tsien

Benjamin Tsien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pre-coherence channel
    Patent number: 7769956
    Abstract: A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies. More particularly, embodiments of the invention include multiple cache agents that each communication with the same protocol agent. In one embodiment, a pre-coherence channel couples the cache agents to the protocol agent to enable the protocol agent to receive events corresponding to cache operations from the cache agents to maintain ordering with respect to the cache operation events.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: August 3, 2010
    Assignee: Intel Corporation
    Inventor: Benjamin Tsien
  • EARLY ISSUE OF TRANSACTION ID
    Publication number: 20100023945
    Abstract: Early issue of transaction ID is disclosed. An apparatus comprising decoder to generate a first node ID indicative of the destination of a cache transaction from a caching agent, a transaction ID allocation logic coupled to and operating in parallel to the decoder to select a transaction ID (TID) for the transaction based on the first node ID, a packet creation unit to create a packet that includes the transaction, the first node ID, the TID and a second node ID corresponding to the requestor.
    Type: Application
    Filed: October 6, 2009
    Publication date: January 28, 2010
    Inventor: Benjamin Tsien
  • Remote hit predictor
    Patent number: 7640401
    Abstract: In one embodiment, a first node comprises at least one memory request source and a node controller coupled to the memory request source. The node controller comprises a remote hit predictor configured to predict a second node to have a coherent copy of a block addressed by a memory request generated by the memory request source, and the node controller is configured to issued a speculative probe to the second node responsive to the prediction and to the memory request.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: December 29, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Benjamin Tsien
  • Early issue of transaction ID
    Patent number: 7620694
    Abstract: Early issue of transaction ID is disclosed. An apparatus comprising decoder to generate a first node ID indicative of the destination of a cache transaction from a caching agent, a transaction ID allocation logic coupled to and operating in parallel to the decoder to select a transaction ID (TID) for the transaction based on the first node ID, a packet creation unit to create a packet that includes the transaction, the first node ID, the TID and a second node ID corresponding to the requestor.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: November 17, 2009
    Assignee: Intel Corporation
    Inventor: Benjamin Tsien
  • Two-Hop Source Snoop Based Messaging Protocol
    Publication number: 20090198913
    Abstract: A messaging protocol that facilitates a distributed cache coherency conflict resolution in a multi-node system that resolves conflicts at a home node. The protocol may perform a method including supporting at least three protocol classes for the messaging protocol, via at least three virtual channels provided by a link layer of a network fabric coupled to the caching agents, wherein the virtual channels include a first virtual channel to support a probe message class, a second virtual channel to support an acknowledgment message class, and a third virtual channel to support a response message class.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 6, 2009
    Inventors: Brannon J. Batson, Benjamin Tsien, William A. Welch
  • Interconnect transaction translation technique
    Patent number: 7546421
    Abstract: A technique to reduce and simplify interconnect traffic within a multi-core processor. At least one embodiment translates two or more system operations destined for a processor core within a multi-core processor into a fewer number of operations to be delivered to the processor core and translates a response from the core into two or more system response operations corresponding to the two or more system operations.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: June 9, 2009
    Assignee: Intel Corporation
    Inventor: Benjamin Tsien
  • Two-hop source snoop based cache coherence protocol
    Patent number: 7543115
    Abstract: A method for cache coherency in a network of a plurality of caching agents includes storing a plurality of miss requests, transmitting the miss requests into the network, sending a probe message on a probe channel and a request message on a second channel from one of the plurality of caching agents, and maintaining an open status for the miss request until the requesting cache agent receives the data or an ownership indicator.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: June 2, 2009
    Assignee: Intel Corporation
    Inventors: Brannon Batson, Benjamin Tsien, William A. Welch
  • Two-hop source snoop based messaging protocol
    Patent number: 7512741
    Abstract: A messaging protocol that facilitates a distributed cache coherency conflict resolution in a multi-node system that resolves conflicts at a home node. The protocol may perform a method including supporting at least three protocol classes for the messaging protocol, via at least three virtual channels provided by a link layer of a network fabric coupled to the caching agents, wherein the virtual channels include a first virtual channel to support a probe message class, a second virtual channel to support an acknowledgment message class, and a third virtual channel to support a response message class.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: March 31, 2009
    Assignee: Intel Corporation
    Inventors: Brannon Batson, Benjamin Tsien, William A. Welch
  • HIDING CONFLICT, COHERENCE COMPLETION AND TRANSACTION ID ELEMENTS OF A COHERENCE PROTOCOL
    Publication number: 20090037665
    Abstract: According to one embodiment of the invention, an apparatus having one or more cache agents and a protocol agent is disclosed. The protocol agent is coupled to the one or more cache agents to receive events corresponding to cache operations from the one or more cache agents to maintain ordering with respect to the cache operation events. The protocol agent includes a structure to handle conflict resolution.
    Type: Application
    Filed: October 14, 2008
    Publication date: February 5, 2009
    Applicant: INTEL CORPORATION
    Inventor: Benjamin Tsien
  • Hiding conflict, coherence completion and transaction ID elements of a coherence protocol
    Patent number: 7437518
    Abstract: An apparatus having one or more cache agents and a protocol agent is disclosed. The protocol agent is coupled to the one or more cache agents to receive events corresponding to cache operations from the one or more cache agents to maintain ordering with respect to the cache operation events. The protocol agent includes a structure to handle conflict resolution.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: October 14, 2008
    Assignee: Intel Corporation
    Inventor: Benjamin Tsien
  • Remote Hit Predictor
    Publication number: 20080243739
    Abstract: In one embodiment, a first node comprises at least one memory request source and a node controller coupled to the memory request source. The node controller comprises a remote hit predictor configured to predict a second node to have a coherent copy of a block addressed by a memory request generated by the memory request source, and the node controller is configured to issued a speculative probe to the second node responsive to the prediction and to the memory request.
    Type: Application
    Filed: March 26, 2007
    Publication date: October 2, 2008
    Inventor: Benjamin Tsien
  • Ring interconnect with multiple coherence networks
    Patent number: 7406566
    Abstract: A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies, while reducing power within an integrated circuit. More particularly, embodiments of the invention include a plurality of cache agents that each communication with the same protocol agent, which may or may not be integrated within any one of the cache agents. Embodiments of the invention also include protocol agents capable of storing multiple sets of data from different sets of cache agents within the same clock cycle.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventor: Benjamin Tsien
  • Buffer allocation for split data messages
    Patent number: 7406568
    Abstract: A technique to store a plurality of addresses and data to address and data buffers, respectively, in an ordered manner. More particularly, one embodiment of the invention stores a plurality of addresses to a plurality of address buffer entries and a plurality of data to a plurality of data buffer entries according to a true least-recently-used (LRU) allocation algorithm.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventor: Benjamin Tsien
  • Snoop processing for multi-processor computing system
    Publication number: 20070073979
    Abstract: A method is described that involves receiving, from a network, a snoop request at a network ordering point and storing the snoop request into a buffer. The snoop request is part of a transaction. The method also involves issuing the snoop request from the buffer and snooping a cache with the snoop request to generate a snoop response. The method also involves, after the snooping, determining if the snoop response's transaction is in conflict with another transaction.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Inventor: Benjamin Tsien
  • Early issue of transaction ID
    Publication number: 20070073856
    Abstract: Early issue of transaction ID is disclosed. An apparatus comprising decoder to generate a first node ID indicative of the destination of a cache transaction from a caching agent, a transaction ID allocation logic coupled to and operating in parallel to the decoder to select a transaction ID (TID) for the transaction based on the first node ID, a packet creation unit to create a packet that includes the transaction, the first node ID, the TID and a second node ID corresponding to the requestor.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 29, 2007
    Inventor: Benjamin Tsien
  • Pre-coherence channel
    Publication number: 20070055828
    Abstract: A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies. More particularly, embodiments of the invention include multiple cache agents that each communication with the same protocol agent. In one embodiment, a pre-coherence channel couples the cache agents to the protocol agent to enable the protocol agent to receive events corresponding to cache operations from the cache agents to maintain ordering with respect to the cache operation events.
    Type: Application
    Filed: September 7, 2005
    Publication date: March 8, 2007
    Inventor: Benjamin Tsien
  • Hiding conflict, coherence completion and transaction ID elements of a coherence protocol
    Publication number: 20070055827
    Abstract: An apparatus having one or more cache agents and a protocol agent is disclosed. The protocol agent is coupled to the one or more cache agents to receive events corresponding to cache operations from the one or more cache agents to maintain ordering with respect to the cache operation events. The protocol agent includes a structure to handle conflict resolution.
    Type: Application
    Filed: September 7, 2005
    Publication date: March 8, 2007
    Inventor: Benjamin Tsien
  • Interconnect transaction translation technique
    Publication number: 20070033347
    Abstract: A technique to reduce and simplify interconnect traffic within a multi-core processor. At least one embodiment translates two or more system operations destined for a processor core within a multi-core processor into a fewer number of operations to be delivered to the processor core and translates a response from the core into two or more system response operations corresponding to the two or more system operations.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 8, 2007
    Inventor: Benjamin Tsien
  • Buffer allocation for split data messages
    Publication number: 20060288171
    Abstract: A technique to store a plurality of addresses and data to address and data buffers, respectively, in an ordered manner. More particularly, one embodiment of the invention stores a plurality of addresses to a plurality of address buffer entries and a plurality of data to a plurality of data buffer entries according to a true least-recently-used (LRU) allocation algorithm.
    Type: Application
    Filed: June 20, 2005
    Publication date: December 21, 2006
    Inventor: Benjamin Tsien
  • Memory attribute speculation
    Publication number: 20060282645
    Abstract: A technique to speculatively assign a memory attribute. More specifically, embodiments of the invention include an architecture to assign and issue a speculative memory attribute based on a plurality of translation look-aside buffer (TLB) page attributes concurrently with the determination of the correct memory attribute, such that, in at least one case, determination of the correct memory attribute does not impact performance of a system in which at least one embodiment of the invention is included.
    Type: Application
    Filed: June 14, 2005
    Publication date: December 14, 2006
    Inventor: Benjamin Tsien