Abstract: The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit can be introduced or additionally multiple SCRs can be coupled inherent through a common base.

Abstract: The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.

Abstract: The present invention provides an ESD device to reduce the total triggering current without increasing the overshoot voltage. This is achieved by localizing the triggering current, such that the local current density remains high enough to trigger the ESD device. This localized triggering provides a fast and efficient triggering of the ESD device.

Abstract: The present invention provides an ESD protection device having at least one diode in a well of first conductivity type formed in a substrate of second conductivity type. The circuit further includes a guard band of the first conductivity surrounding at least a portion of the diode, thus forming an NPN transistor between diode cathode, the substrate and the guard-band.

Abstract: The present invention provides a charged-device model (CDM) electrostatic discharge (ESD) protection circuit for an integrated circuit (IC). The ESD protection circuit comprises a substrate of first conductivity type; a MOS component of second conductivity type formed on a first well on the substrate, and coupled to a pad; an isolating well/region having the second conductivity type being formed between the first well and the substrate to separate the first well and the substrate. Additionally, the circuit comprises an ESD clamp coupled to the isolated well/region. Under normal power operation, the ESD clamp is open. During a CDM ESD event, the CDM charges accumulated in the substrate and the MOS component are removed by the ESD clamp to prevent damage to the IC.

Abstract: An apparatus having an inter-domain electrostatic discharge (ESD) protection circuit for protection of an integrated circuit (IC) with multiple power domains. The protection circuit in response to an ESD event provides an ESD protection between different power domains. Specifically, the protection circuit comprises at least one clamp coupled to one power domain, which conducts current during an ESD event to provide extra current in the interface line between the two different power domains. This extra current also in turn increases the voltage over the impedance element on the interface line, thus improving the design margins for the ESD protection and providing a better ESD protection capability for IC products.

Abstract: The present invention provides an integrated circuit for providing ESD protection. The integrated circuit comprises a transistor device having at least one interleaved finger having a substrate region, a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further comprises at least one highly doped junction formed adjacent to the source region to measure voltage potential of the substrate region. The integrated circuit further comprises a switching circuit coupled to the at least one highly doped junction such that the voltage potential is transferred to the switching circuit to either draw the full ESD current or trigger to draw the full ESD current.

Abstract: The present invention provides a semiconductor structure device having a first and a second semiconductor devices with a silicon controlled rectifier (SCR) formed between the two devices with advantages to couple the devices to provide more design flexibility and enhanced triggering in order to improve the ESD performance of the device.

Abstract: The present invention provides an ESD protection circuitry in a semiconductor integrated circuit (IC) having protected circuitry to prevent false triggering of the ESD clamp. The circuitry includes an SCR as an ESD clamp having an anode adapted for coupling to a first voltage source, and a cathode adapted for coupling to a second voltage source. The circuitry also includes at least one noise current buffer (NCB) coupled between at least one of a first trigger tap of the SCR and the first voltage source such that the first trigger tap of the SCR is coupled to a power supply.

Abstract: The present invention provides an ESD protection circuit for a ESD clamp such as an SCR in the protection of an integrated circuit. In one embodiment of the invention, the SCR having at least one interspersed high-doped first region formed within a first lightly doped region and at least one interspersed high-doped second region formed within a second lightly doped region. The circuit further comprising at least one guardring connected to at least one trigger tap of the SCR to collect the ESD current to provide for a fast and easier triggering of the SCR.

Abstract: The present invention provides an improvement on ESD protection circuitry by controlling the trigger circuit to prevent the unwanted triggering of the device. The circuitry includes an ESD clamp with a trigger circuit coupled to the clamp. Both the clamp and the trigger circuit are coupled to a first reference potential. The circuitry also includes a control line coupled to the trigger circuit. The control line is coupled to a second reference potential to further control the behavior of the trigger circuit such that when the power is supplied to the second reference potential, the control line disables the trigger circuit, and when power is not supplied to the second reference potential, the control line enables the trigger circuit.

Abstract: A method and apparatus for providing ESD event protection for a circuit using a source or bulk pump to increase the bulk and/or source potential level during an ESD event. The apparatus comprises a protection circuit that, in response to an ESD event, limits the voltage formed between two terminals of a transistor by adjusting a potential level on the second terminal.

Abstract: The present invention provides a MOS transistor device for providing ESD protection comprising at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further comprises at least one isolation gate formed in at least one of the interleaved fingers. The device can further comprises a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.

Abstract: The present invention provides an integrated circuit for improved ESD protection and method of forming the same. The integrated circuit comprises a substrate and an insulating layer formed over the substrate. The circuit also comprises a field effect field effect transistor (FET) formed over the insulating layer. The FET includes a well region of a first conductivity type. The circuit also includes a well resistor coupled to the FET to provide ballasting to the circuit. The well resistor includes a well region also of the first conductivity type.

Abstract: The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit can be introduced or additionally multiple SCRs can be coupled inherent through a common base.

Abstract: The present invention provides a semiconductor structure device having a first and a second semiconductor devices with a silicon controlled rectifier (SCR) formed between the two devices with advantages to couple the devices to provide more design flexibility and enhanced triggering in order to improve the ESD performance of the device.

Abstract: A method and apparatus for providing ESD protection. An ESD clamp is connected across the terminals to be protected circuit. The clamp is coupled to a current detector that activates the clamp when current from an ESD event exceeds a predefined limit.

Abstract: A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device.

Abstract: The invention provides a method of inducing an effective immune response to pathogenic lymphocytes by administering dendritic cells previously pulsed with the idiotype protein of interest. In one embodiment, a method for the active immunization of a mammal against lymphoma is provided. This embodiment comprises exposing dendritic cells to idiotype Ig to make idiotype pulsed dendritic cells and injecting the idiotype pulsed dendritic cells back into the mammal, whereby immunity against lymphoma cells is induced. In another embodiment, the invention relates to the administration of both idiotypic cells and pulsed dendritic cells.