Patents by Inventor Benoit de Lescure
Benoit de Lescure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210149836Abstract: Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses. The transactions originate from a master and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the master. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple slaves. The slaves send a response, which is transported back by the NoC to the corresponding master.Type: ApplicationFiled: November 15, 2019Publication date: May 20, 2021Applicant: ARTERIS, INC.Inventors: Syed Ijlal SHAH, John CODDINGTON, Benoit de LESCURE
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Patent number: 10990724Abstract: Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.Type: GrantFiled: December 27, 2019Date of Patent: April 27, 2021Assignee: ARTERIS, INC.Inventors: Moez Cherif, Benoit De Lescure
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Patent number: 10902166Abstract: A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.Type: GrantFiled: December 13, 2018Date of Patent: January 26, 2021Assignee: ARTERIS, INC.Inventors: Benoit de Lescure, Alexis Boutiller
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Publication number: 20200193077Abstract: A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Applicant: ARTERIS, INC.Inventors: Alexis BOUTILLER, Benoit de LESCURE
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Patent number: 10452499Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.Type: GrantFiled: July 16, 2018Date of Patent: October 22, 2019Assignee: ARTERIS, INC.Inventors: Benoit de Lescure, Jean Philippe Loison, Alexis Boutiller
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Publication number: 20190205489Abstract: A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.Type: ApplicationFiled: December 13, 2018Publication date: July 4, 2019Applicant: Arteris, Inc.Inventors: Benoit de LESCURE, Alexis BOUTILLER
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Patent number: 10268794Abstract: A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited by a user. Statistical metrics are calculated, including wire length, switch area, NoC area, and maximum signal propagation delay for logic in each of multiple clock domains. Wire density can also be overlaid on chip's floorplan on the display. The NoC topology is represented by a data structure indicating connections between initiator and target endpoints with ordered lists of switches in between. The data structures are written and read from memory or a non-transient computer readable medium. The locations of endpoint and switches are also written out, as scripts for place & route tools.Type: GrantFiled: March 26, 2018Date of Patent: April 23, 2019Assignee: ARTERIS, Inc.Inventor: Benoit de Lescure
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Publication number: 20180322021Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents.Type: ApplicationFiled: July 16, 2018Publication date: November 8, 2018Applicant: Arteris, Inc.Inventors: Benoit de LESCURE, Jean Philippe LOISON, Alexis BOUTILLER
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Publication number: 20180218105Abstract: A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited by a user. Statistical metrics are calculated, including wire length, switch area, NoC area, and maximum signal propagation delay for logic in each of multiple clock domains. Wire density can also be overlaid on chip's floorplan on the display. The NoC topology is represented by a data structure indicating connections between initiator and target endpoints with ordered lists of switches in between. The data structures are written and read from memory or a non-transient computer readable medium. The locations of endpoint and switches are also written out, as scripts for place & route tools.Type: ApplicationFiled: March 26, 2018Publication date: August 2, 2018Applicant: Arteris, Inc.Inventor: Benoit de LESCURE
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Patent number: 10025677Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.Type: GrantFiled: December 21, 2016Date of Patent: July 17, 2018Assignee: ARTERIS, Inc.Inventors: Benoit de Lescure, Jean Philippe Loison, Alexis Boutiller
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Publication number: 20180173597Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Applicant: Arteris, Inc.Inventors: Benoit de LESCURE, Jean Philippe LOISON, Alexis BOUTILLER
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Patent number: 9940423Abstract: A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited by a user. Statistical metrics are calculated, including wire length, switch area, NoC area, and maximum signal propagation delay for logic in each of multiple clock domains. Wire density can also be overlaid on chip's floorplan on the display. The NoC topology is represented by a data structure indicating connections between initiator and target endpoints with ordered lists of switches in between. The data structures are written and read from memory or a non-transient computer readable medium. The locations of endpoint and switches are also written out, as scripts for place & route tools.Type: GrantFiled: December 20, 2015Date of Patent: April 10, 2018Assignee: ARTERIS, Inc.Inventor: Benoit de Lescure
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Publication number: 20170177778Abstract: A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited by a user. Statistical metrics are calculated, including wire length, switch area, NoC area, and maximum signal propagation delay for logic in each of multiple clock domains. Wire density can also be overlaid on chip's floorplan on the display. The NoC topology is represented by a data structure indicating connections between initiator and target endpoints with ordered lists of switches in between. The data structures are written and read from memory or a non-transient computer readable medium. The locations of endpoint and switches are also written out, as scripts for place & route tools.Type: ApplicationFiled: December 20, 2015Publication date: June 22, 2017Applicant: Arteris, Inc.Inventor: Benoit de LESCURE
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Patent number: 9310867Abstract: A method, apparatus, and system in which an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, including a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; wherein the power manager has its own dedicated CPU or dedicated state machine to execute power management instructions; and wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.Type: GrantFiled: July 29, 2013Date of Patent: April 12, 2016Assignee: Sonics, Inc.Inventors: Raymond G. Brinks, Benoit de Lescure, Stephen W. Hamilton
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Patent number: 8601288Abstract: A method, apparatus, and system in which an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, including a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; wherein the power manager has its own dedicated CPU or dedicated state machine to execute power management instructions; and wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.Type: GrantFiled: August 31, 2010Date of Patent: December 3, 2013Assignee: Sonics, Inc.Inventors: Ray Brinks, Benoit de Lescure
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Publication number: 20130311796Abstract: A method, apparatus, and system in which an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, including a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; wherein the power manager has its own dedicated CPU or dedicated state machine to execute power management instructions; and wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.Type: ApplicationFiled: July 29, 2013Publication date: November 21, 2013Applicant: Sonics, Inc.Inventors: Raymond G. Brinks, Benoit de Lescure, Stephen W. Hamilton
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Patent number: 8438306Abstract: A method, apparatus, and system for providing layer concurrency connecting two or more master Intellectual Property cores to a Network on a Chip (NoC) for an integrated circuit is provided. An embodiment includes two masters connected using a common tightly coupled protocol to a first interface of an NoC. A protocol conversion unit can be coupled between the two or more masters and the NoC to convert a request in the tightly coupled protocol to a decoupled protocol that decouples request phasing from response phasing and then passes the request in the decoupled protocol format onto the NoC. The system also provides for arbitration amongst the two or more masters. Requests from the masters are still in the common tightly coupled protocol and are translated by the protocol conversion unit into a request in a decoupled protocol to enable out of order return of responses.Type: GrantFiled: November 2, 2010Date of Patent: May 7, 2013Assignee: Sonics, Inc.Inventors: Benoit De Lescure, Krishnan Srinivasan
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Publication number: 20120110106Abstract: A method, apparatus, and system for providing layer concurrency connecting two or more master Intellectual Property cores to a Network on a Chip (NoC) for an integrated circuit is provided. An embodiment includes two masters connected using a common tightly coupled protocol to a first interface of an NoC. A protocol conversion unit can be coupled between the two or more masters and the NoC to convert a request in the tightly coupled protocol to a decoupled protocol that decouples request phasing from response phasing and then passes the request in the decoupled protocol format onto the NoC. The system also provides for arbitration amongst the two or more masters. Requests from the masters are still in the common tightly coupled protocol and are translated by the protocol conversion unit into a request in a decoupled protocol to enable out of order return of responses.Type: ApplicationFiled: November 2, 2010Publication date: May 3, 2012Applicant: SONICS, INC.Inventors: BENOIT DE LESCURE, KRISHNAN SRINIVASAN
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Publication number: 20120054511Abstract: A method, apparatus, and system in which an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, including a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; wherein the power manager has its own dedicated CPU or dedicated state machine to execute power management instructions; and wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Applicant: SONICS, INCInventors: Ray Brinks, Benoit de Lescure