Abstract: A method and circuit for testing phase interpolators is provided. The method performs a sweep over a phase interpolator delay range and detects if the phase interpolators experience an unacceptably large non-linearity which leads to inaccurate clock timing. The testing circuit implementing this technique uses a phase detector to detect a fault, and in one embodiment, an additional phase interpolator is added as well.

Abstract: A circuit for testing phase detectors in a delay locked loop is provided. The circuit uses a second phase detector arranged to receive the signals entering a first phase detector. Particularly, the circuit is routed such that a signal entering the D input of the first phase detector is inputted into the clock input of the second phase detector, and a signal entering the clock input of the first phase detector is inputted into the D input of the second phase detector. The circuit is also coupled to a test controller located on-die or at a high volume manufacturing (HVM) tester.

Abstract: A circuit for testing phase detectors in a delay locked loop is provided. The circuit uses a second phase detector arranged to receive the signals entering a first phase detector. Particularly, the circuit is routed such that a signal entering the D input of the first phase detector is inputted into the clock input of the second phase detector, and a signal entering the clock input of the first phase detector is inputted into the D input of the second phase detector. The circuit is also coupled to a test controller located on-die or at a high volume manufacturing (HVM) tester.

Abstract: A method and circuit for testing phase detectors in a delay locked loop is provided. The method includes storing output from a first phase detector and from a second phase detector when the counter is at the +0, +1, and ?1 counter positions, and comparing the results to determine whether a phase detector is faulty. The circuit implementing this technique uses a second phase detector configured to receive the signals entering a first phase detector. Particularly, the circuit is routed such that a signal entering the D input of the first phase detector is inputted into the clock input of the second phase detector, and a signal entering the clock input of the first phase detector is inputted into the D input of the second phase detector. The circuit is also coupled to a test controller located on-die or at a high volume manufacturing (HVM) tester.

Abstract: A method and circuit for testing phase detectors in a delay locked loop is provided. The method includes storing output from a first phase detector and from a second phase detector when the counter is at the +0, +1, and ?1 counter positions, and comparing the results to determine whether a phase detector is faulty. The circuit implementing this technique uses a second phase detector configured to receive the signals entering a first phase detector. Particularly, the circuit is routed such that a signal entering the D input of the first phase detector is inputted into the clock input of the second phase detector, and a signal entering the clock input of the first phase detector is inputted into the D input of the second phase detector. The circuit is also coupled to a test controller located on-die or at a high volume manufacturing (HVM) tester.

Abstract: A method and circuit for testing phase interpolators is provided. The method performs a sweep over a phase interpolator delay range and detects if the phase interpolators experience an unacceptably large non-linearity which leads to inaccurate clock timing. The testing circuit implementing this technique uses a phase detector to detect a fault, and in one embodiment, an additional phase interpolator is added as well.