Abstract: A clock and data recovery device (CDR) based on multi-rate multi-phase oversampling technique is capable of receiving serial data streams of different data rates. The CDR uses a multi-rate multi-phase oversampling technique. N phase shifted clocks are generated based on a single clock and rising edges (or falling) of the phase shifted clocks and define N sampling points where a serial data stream is sampled. The multi-phase oversampling technique provides at least two sampling points per data bit of the serial data stream at highest data rates. The sampling points divide one clock cycle of the single clock into N zones. Depending on which of the zones a data edge transition is detected, the CDR can converge the sampling points to optimal data sampling positions in the serial data stream.

Abstract: An adaptive equalizer may use dual loop adaptation to improve the performance of the equalizer. The first feedback loop may generate a boost control signal, based on the signal input to and output from a slicer. A second feedback loop may correct the swing amplitude of the slicer, so that the swing of the output matches the swing of the input.

Abstract: A serial data link, which derives an incoming data clock linked to the data rate of the incoming data, also generates an outgoing data clock that is used to re-transmit the data from the serial link into the communications channel. The incoming and outgoing data clocks are derived from a single local oscillator, using dual phase interpolating circuits to adjust the phase lead/lag to match the incoming data rate.

Abstract: A clock and data recovery device (CDR) based on multi-rate multi-phase oversampling technique is capable of receiving serial data streams of different data rates. The CDR uses a multi-rate multi-phase oversampling technique. N phase shifted clocks are generated based on a single clock and rising edges (or falling) of the phase shifted clocks and define N sampling points where a serial data stream is sampled. The multi-phase oversampling technique provides at least two sampling points per data bit of the serial data stream at highest data rates. The sampling points divide one clock cycle of the single clock into N zones. Depending on which of the zones a data edge transition is detected, the CDR can converge the sampling points to optimal data sampling positions in the serial data stream.