Patents by Inventor Beom-Jin PARK
Beom-Jin PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240186392Abstract: A semiconductor device including a substrate, a first and second active pattern extending in a first horizontal direction on the substrate, the second active pattern apart from the first active pattern in the first horizontal direction, first nanosheets apart from each other in a vertical direction on the first active pattern, second nanosheets apart from each other in the vertical direction on the first and second active patterns, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the first active pattern and surrounding the first nanosheets, a source/drain region between the first and second nanosheets, an active cut penetrating the second nanosheets in the vertical direction, extending to the substrate, and separating the first and second active patterns, and a sacrificial layer between the source/drain region and the active cut, in contact with the active cut, and including silicon germanium may be provided.Type: ApplicationFiled: December 6, 2022Publication date: June 6, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Beom Jin PARK, Myung Gil Kang, Dong Won Kim, Keun Hwi Cho
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Publication number: 20240099467Abstract: The present invention relates to a prefabricated chair and, more particularly, to a prefabricated chair separated into two frames so that the volume thereof can be remarkably reduced, thereby facilitating storage and transportation and enabling easy assembly without a separate tool.Type: ApplicationFiled: April 18, 2022Publication date: March 28, 2024Inventor: Beom Jin PARK
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Patent number: 11923362Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.Type: GrantFiled: May 9, 2023Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
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Patent number: 11923456Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.Type: GrantFiled: April 18, 2022Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Gil Yang, Beom-Jin Park, Seung-Min Song, Geum-Jong Bae, Dong-Il Bae
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Patent number: 11843000Abstract: A semiconductor device that reduces the occurrence of a leakage current by forming a doped layer in each of an NMOS region and a PMOS region on an SOI substrate, and completely separating the doped layer of the NMOS region from the doped layer of the PMOS region using the element isolation layer is provided. The semiconductor device includes a first region and a second region adjacent to the first region, a substrate including a first layer, an insulating layer on the first layer, and a second layer on the insulating layer, a first doped layer on the second layer in the first region and including a first impurity, a second doped layer on the second layer in the second region and including a second impurity different from the first impurity, and an element isolation layer configured to separate the first doped layer from the second doped layer, and in contact with the insulating layer.Type: GrantFiled: June 2, 2021Date of Patent: December 12, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Beom Jin Park, Myung Gil Kang, Dong Won Kim, Keun Hwi Cho
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Publication number: 20230282642Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.Type: ApplicationFiled: May 9, 2023Publication date: September 7, 2023Applicant: SAMSUNG ELECTRONICS JCO., LTD.Inventors: Myung-gil KANG, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
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Patent number: 11676964Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.Type: GrantFiled: August 12, 2022Date of Patent: June 13, 2023Assignee: SAMSUNG ELECTRONICS CO.. LTD.Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-Won Kim, Jung-gil Yang
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Publication number: 20230170386Abstract: A semiconductor device includes first to fourth active patterns extending in a horizontal first direction. The second active pattern is spaced apart from the first active pattern in the first direction. The third active pattern is spaced apart from the first active pattern in a horizontal second direction. The fourth active pattern is spaced apart from the third active pattern in the first direction. A field insulating layer surrounds a sidewall of each of the first to fourth active patterns. First to fourth pluralities of nanosheets are respectively disposed the first to fourth active patterns. A first gate electrode extends in the second direction, intersects each of the first and third active patterns, and surrounds the first and third pluralities of nanosheets. A second gate electrode extends in the second direction, intersects each of the second and fourth active patterns, and surrounds the second and fourth pluralities of nanosheets.Type: ApplicationFiled: August 16, 2022Publication date: June 1, 2023Inventors: Ho Jin LEE, Beom Jin PARK, Myoung Sun LEE, Keun Hwi CHO, Dong Won KIM
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Publication number: 20220384432Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.Type: ApplicationFiled: August 12, 2022Publication date: December 1, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
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Patent number: 11444081Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.Type: GrantFiled: January 15, 2021Date of Patent: September 13, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
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Publication number: 20220238707Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.Type: ApplicationFiled: April 18, 2022Publication date: July 28, 2022Inventors: Jung-Gil YANG, Beom-Jin PARK, Seung-Min SONG, Geum-Jong BAE, Dong-Il BAE
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Publication number: 20220130865Abstract: A semiconductor device that reduces the occurrence of a leakage current by forming a doped layer in each of an NMOS region and a PMOS region on an SOT substrate, and completely separating the doped layer of the NMOS region from the doped layer of the PMOS region using the element isolation layer is provided. The semiconductor device includes a first region and a second region adjacent to the first region, a substrate including a first layer, an insulating layer on the first layer, and a second layer on the insulating layer, a first doped layer on the second layer in the first region and including a first impurity, a second doped layer on the second layer in the second region and including a second impurity different from the first impurity, and an element isolation layer configured to separate the first doped layer from the second doped layer, and in contact with the insulating layer.Type: ApplicationFiled: June 2, 2021Publication date: April 28, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Beom Jin PARK, Myung Gil KANG, Dong Won KIM, Keun Hwi CHO
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Patent number: 11309421Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.Type: GrantFiled: March 12, 2020Date of Patent: April 19, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Gil Yang, Beom-Jin Park, Seung-Min Song, Geum-Jong Bae, Dong-Il Bae
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Publication number: 20210242201Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.Type: ApplicationFiled: January 15, 2021Publication date: August 5, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung-gil KANG, Beom-jin PARK, Geum-jong BAE, Dong-won KIM, Jung-gil YANG
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Patent number: 10930649Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.Type: GrantFiled: March 19, 2019Date of Patent: February 23, 2021Assignee: SAMSUNG ELECTRONICS CO.. LTD.Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
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Publication number: 20200220006Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.Type: ApplicationFiled: March 12, 2020Publication date: July 9, 2020Inventors: JUNG-GIL YANG, Beom-Jin Park, Seung-Min Song, Geum-Jong Bae, Dong-Il Bae
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Patent number: 10629740Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.Type: GrantFiled: August 28, 2018Date of Patent: April 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Gil Yang, Beom-Jin Park, Seung-Min Song, Geum-Jong Bae, Dong-Il Bae
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Publication number: 20200083219Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.Type: ApplicationFiled: March 19, 2019Publication date: March 12, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
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Patent number: 10497804Abstract: A vertical transistor structure includes a first transistor and a second transistor. The first transistor includes a first lower electrode connected to a second upper electrode of the second transistor, and a second upper electrode connected to a first lower electrode of the second transistor. The first transistor also includes a gate electrode connected to a gate electrode of the second transistor.Type: GrantFiled: August 7, 2017Date of Patent: December 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Il Park, Beom-Jin Park, Yun-Il Lee, Jung-Gun You, Dong-Hun Lee
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Publication number: 20190157444Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.Type: ApplicationFiled: August 28, 2018Publication date: May 23, 2019Inventors: Jung-Gil Yang, Beom-Jin Park, Seung-Min Song, Geum-Jong Bae, Dong-Il Bae