Patents by Inventor Berinder Brar
Berinder Brar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110220967Abstract: A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound.Type: ApplicationFiled: May 24, 2011Publication date: September 15, 2011Applicant: Teledyne Licensing, LLCInventors: Gerard J. Sullivan, Amal Ikhlassi, Joshua I. Bergman, Berinder Brar, Gabor Nagy
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Patent number: 7989842Abstract: The disclosure relates to a zero-bias heterojunction diode detector with varying impedance. The detector includes a substrate supporting a Schottky structure and an Ohmic contact layer. A metallic contact layer is formed over the Ohmic layer. The Schottky structure comprises a plurality of barrier layers and each of the plurality of barriers layers includes a first material and a second material. In one embodiment, the composition percentage of the second material in each of the barrier layers increases among the plurality of barrier layers from the substrate to the metal layer in order to provide a graded periodicity for the Schottky structure.Type: GrantFiled: February 27, 2009Date of Patent: August 2, 2011Assignee: Teledyne Scientific & Imaging, LLCInventors: Hooman Kazemi, Chanh Nguyen, Berinder Brar
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Publication number: 20110143518Abstract: A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate having a first end and a second end, a conducting layer above the first end of the substrate, an isolation implant providing lateral isolation in the conducting layer, a first active layer deposited above the conducting layer and configured for the low-noise amplifier, and a buffer layer deposited above the conducting layer and configured for the low-noise amplifier.Type: ApplicationFiled: February 22, 2011Publication date: June 16, 2011Inventors: Berinder Brar, Joshua I. Bergman, Amal Ikhlassi, Gabor Nagy, Gerard J. Sullivan
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Publication number: 20110031531Abstract: A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound.Type: ApplicationFiled: September 24, 2010Publication date: February 10, 2011Inventors: Gerard J. Sullivan, Amal Ikhlassi, Joshua I. Bergman, Berinder Brar, Gabor Nagy
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Publication number: 20110018034Abstract: A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate having a first end and a second end, a conducting layer above the first end of the substrate, an isolation implant providing lateral isolation in the conducting layer, a first active layer deposited above the conducting layer and configured for the low-noise amplifier, and a buffer layer deposited above the conducting layer and configured for the low-noise amplifier.Type: ApplicationFiled: August 31, 2010Publication date: January 27, 2011Inventors: Berinder Brar, Joshua I. Bergman, Amal Ikhlassi, Gabor Nagy, Gerard J. Sullivan
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Patent number: 7820541Abstract: A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound.Type: GrantFiled: September 14, 2006Date of Patent: October 26, 2010Assignee: Teledyne Licensing, LLCInventors: Gerard J. Sullivan, Amal Ikhlassi, Joshua I. Bergman, Berinder Brar, Gabor Nagy
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Patent number: 7808016Abstract: A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate wafer having a first end and a second end, a conducting layer above the first end of the substrate wafer, an isolation implant providing lateral isolation in the conducting layer, a first active layer deposited above the conducting layer and configured for the low-noise amplifier, and a buffer layer deposited above the conducting layer and configured for the low-noise amplifier.Type: GrantFiled: September 14, 2006Date of Patent: October 5, 2010Assignee: Teledyne Licensing, LLCInventors: Berinder Brar, Joshua I. Bergman, Amal Ikhlassi, Gabor Nagy, Gerard J. Sullivan
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Publication number: 20100219449Abstract: The disclosure relates to a zero-bias heterojunction diode detector with varying impedance. The detector includes a substrate supporting a Schottky structure and an Ohmic contact layer. A metallic contact layer is formed over the Ohmic layer. The Schottky structure comprises a plurality of barrier layers and each of the plurality of barriers layers includes a first material and a second material. In one embodiment, the composition percentage of the second material in each of the barrier layers increases among the plurality of barrier layers from the substrate to the metal layer in order to provide a graded periodicity for the Schottky structure.Type: ApplicationFiled: February 27, 2009Publication date: September 2, 2010Applicant: TELEDYNE SCIENTIFIC & IMAGING, LLCInventors: Hooman Kazemi, Chanh Nguyen, Berinder Brar
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Patent number: 7518165Abstract: A metamorphic high electron mobility transistor having a plurality of high electron mobility transistor layers, a semi-insulating substrate, a ternary metamorphic buffer layer positioned between the semi-insulating substrate and the plurality of high electron mobility transistor layers, the ternary metamorphic buffer layer being Al1-xGaxSb such that x is greater than or equal to 0.2 but less than 0.3, a stabilizing layer positioned between the ternary metamorphic buffer layer and the plurality of high electron mobility transistor layers, the stabilizing layer being Al1-yGaySb such that y is greater than 0.2 but less than or equal to 0.3 and y is greater than x, and a nucleation layer interposed between the semi-insulating substrate and the ternary metamorphic buffer layer.Type: GrantFiled: September 14, 2006Date of Patent: April 14, 2009Assignee: Teledyne Licensing, LLCInventors: Joshua I. Bergman, Berinder Brar, Amal Ikhlassi, Gabor Nagy, Gerard J. Sullivan
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Publication number: 20080067559Abstract: A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate wafer having a first end and a second end, a conducting layer above the first end of the substrate wafer, an isolation implant providing lateral isolation in the conducting layer, a first active layer deposited above the conducting layer and configured for the low-noise amplifier, and a buffer layer deposited above the conducting layer and configured for the low-noise amplifier.Type: ApplicationFiled: September 14, 2006Publication date: March 20, 2008Inventors: Berinder Brar, Joshua I. Bergman, Amal Ikhlassi, Gabor Nagy, Gerard J. Sullivan
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Publication number: 20080070399Abstract: A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound.Type: ApplicationFiled: September 14, 2006Publication date: March 20, 2008Inventors: Gerard J. Sullivan, Amal Ikhlassi, Joshua I. Bergman, Berinder Brar, Gabor Nagy
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Publication number: 20080067547Abstract: A high electron mobility transistor having a first and a second layer with a ternary metamorphic buffer between the first and second layers, the first layer composed of a first material and the second layer composed of a second material, the first and second material having different lattice constants.Type: ApplicationFiled: September 14, 2006Publication date: March 20, 2008Inventors: Joshua I. Bergman, Berinder Brar, Amal Ikhlassi, Gabor Nagy, Gerard J. Sullivan
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Publication number: 20080054304Abstract: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.Type: ApplicationFiled: October 2, 2007Publication date: March 6, 2008Inventors: Mariam Sadaka, Berinder Brar, Wonill Ha, Chanh Nguyen
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Publication number: 20080048173Abstract: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.Type: ApplicationFiled: October 2, 2007Publication date: February 28, 2008Inventors: Mariam Sadaka, Berinder Brar, Wonill Ha, Chanh Nguyen
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Publication number: 20080048219Abstract: A semiconductor device including a substrate-driven field-effect transistor with a lateral channel and a parallel-coupled Schottky diode, and a method of forming the same. In one embodiment, the substrate-driven field-effect transistor of the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof, and a lateral channel above the conductive substrate. The substrate-driven field-effect transistor also includes a second contact above the lateral channel and an interconnect that connects the lateral channel to the conductive substrate operable to provide a low resistance coupling between the first contact and the lateral channel. The semiconductor device also includes a Schottky diode parallel-coupled to the substrate-driven field-effect transistor. A first and second terminal of the Schottky diode are couplable to the first and second contacts, respectively, of the substrate drive field-effect transistor.Type: ApplicationFiled: October 22, 2007Publication date: February 28, 2008Inventors: Berinder Brar, Wonill Ha
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Publication number: 20080048174Abstract: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.Type: ApplicationFiled: October 2, 2007Publication date: February 28, 2008Inventors: Mariam Sadaka, Berinder Brar, Wonill Ha, Chanh Nguyen
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Publication number: 20070187717Abstract: A semiconductor device and method of forming the same. The semiconductor device includes an epitaxially grown and conductive buffer layer having a contact covering a substantial portion of a bottom surface thereof and a lateral channel above the buffer layer. The semiconductor device also includes another contact above the lateral channel and an interconnect that connects the lateral channel to the buffer layer, operable to provide a low resistance coupling between the contact and the lateral channel.Type: ApplicationFiled: April 3, 2007Publication date: August 16, 2007Inventors: Mariam Sadaka, Berinder Brar, Wonill Ha, Chanh Nguyen
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Publication number: 20070145417Abstract: A semiconductor device having a lateral channel with contacts on opposing surfaces thereof. The semiconductor device includes a conductive substrate having a source contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes an isolation layer above the conductive substrate, a lateral channel above the isolation layer and a drain contact above the lateral channel. The semiconductor device further includes a gate located in a gate recess interposed between the lateral channel and the drain contact and a drain formed by at least one source/drain contact layer interposed between the lateral channel and the drain contact. The drain is offset on one side of the gate by a gate-to-drain separation distance. The semiconductor device still further includes an interconnect that connects the lateral channel to the conductive substrate operable to provide a low resistance coupling between the source contact and the lateral channel.Type: ApplicationFiled: February 27, 2007Publication date: June 28, 2007Inventors: Berinder Brar, Wonill Ha, Mariam Sadaka, Chanh Nguyen
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Publication number: 20070069286Abstract: A semiconductor device having at least one lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a lateral channel above the conductive substrate. The semiconductor device further includes a second contact above the lateral channel. The semiconductor device still further includes an interconnect having a sloped wall that connects the lateral channel to the conductive substrate. The interconnect is operable to provide a low resistance coupling between the first contact and the lateral channel. In a related but alternative embodiment, the first contact is a source contact and the second contact is a drain contact for the semiconductor device.Type: ApplicationFiled: September 27, 2005Publication date: March 29, 2007Inventors: Berinder Brar, Wonill Ha, James Vorhaus
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Publication number: 20070051981Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.Type: ApplicationFiled: September 7, 2005Publication date: March 8, 2007Applicant: THE BOEING COMPANYInventor: Berinder Brar