Patents by Inventor Berinder P. S. Brar

Berinder P. S. Brar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8415737
    Abstract: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: April 9, 2013
    Assignee: Flextronics International USA, Inc.
    Inventors: Berinder P. S. Brar, Wonill Ha
  • Patent number: 8043910
    Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: October 25, 2011
    Assignee: The Boeing Company
    Inventor: Berinder P. S. Brar
  • Patent number: 7838905
    Abstract: A semiconductor device having multiple lateral channels with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a first lateral channel above the conductive substrate and a second lateral channel above the first lateral channel. The semiconductor device further includes a second contact above the second lateral channel. The semiconductor device still further includes an interconnect that connects the first and second lateral channels to the conductive substrate operable to provide a low resistance coupling between the first contact and the first and second lateral channels.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: November 23, 2010
    Assignee: Flextronics International USA, Inc.
    Inventors: Berinder P. S. Brar, Wonill Ha
  • Publication number: 20100240187
    Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.
    Type: Application
    Filed: May 28, 2010
    Publication date: September 23, 2010
    Applicant: THE BOEING COMPANY
    Inventor: Berinder P.S. Brar
  • Patent number: 7755106
    Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: July 13, 2010
    Assignee: The Boeing Company
    Inventor: Berinder P. S. Brar
  • Patent number: 7675090
    Abstract: A semiconductor device and method of forming the same. The semiconductor device includes an epitaxially grown and conductive buffer layer having a contact covering a substantial portion of a bottom surface thereof and a lateral channel above the buffer layer. The semiconductor device also includes another contact above the lateral channel and an interconnect that connects the lateral channel to the buffer layer, operable to provide a low resistance coupling between the contact and the lateral channel.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: March 9, 2010
    Assignee: Flextronics International USA, Inc.
    Inventors: Mariam Gergi Sadaka, Berinder P. S. Brar, Wonill Ha, Chanh Ngoc Minh Nguyen
  • Patent number: 7663183
    Abstract: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer within the pillar regions. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: February 16, 2010
    Assignee: Flextronics International USA, Inc.
    Inventors: Berinder P. S. Brar, Wonill Ha
  • Patent number: 7655963
    Abstract: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: February 2, 2010
    Assignee: Flextronics International USA, Inc.
    Inventors: Mariam Gergi Sadaka, Berinder P. S. Brar, Wonill Ha, Chanh Ngoc Minh Nguyen
  • Patent number: 7642568
    Abstract: A semiconductor device including a substrate-driven field-effect transistor with a lateral channel and a parallel-coupled Schottky diode, and a method of forming the same. In one embodiment, the substrate-driven field-effect transistor of the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof, and a lateral channel above the conductive substrate. The substrate-driven field-effect transistor also includes a second contact above the lateral channel and an interconnect that connects the lateral channel to the conductive substrate operable to provide a low resistance coupling between the first contact and the lateral channel. The semiconductor device also includes a Schottky diode parallel-coupled to the substrate-driven field-effect transistor. A first and second terminal of the Schottky diode are couplable to the first and second contacts, respectively, of the substrate drive field-effect transistor.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: January 5, 2010
    Assignee: Flextronics International USA, Inc.
    Inventors: Berinder P. S. Brar, Wonill Ha
  • Patent number: 7564074
    Abstract: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: July 21, 2009
    Assignee: Flextronics International USA, Inc.
    Inventors: Mariam Gergi Sadaka, Berinder P. S. Brar, Wonill Ha, Chanh Ngoc Minh Nguyen
  • Patent number: 7563713
    Abstract: A mask layer is applied to a surface of a semiconductor structure or a seed layer deposited on the surface. The mask layer has a submicron width opening with a high aspect ratio that exposes a portion of the surface or seed layer. Conductive material is conformed to the opening, for example by plating, to form a first contact on the surface or seed layer. The mask and the top layer of the semiconductor structure, except for the portion under the first contact, are removed to expose a second layer of the semiconductor structure. An insulating layer is formed along the sidewalls of the first contact and the top layer of the semiconductor structure beneath the first contact. A mask is then applied to the second layer and a second contact is formed by selectively depositing metal only on the portion of the second layer exposed by the opening.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: July 21, 2009
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: Petra V. Rowell, Miguel E. Urteaga, Richard L. Pierson, Jr., Berinder P. S. Brar
  • Patent number: 7541640
    Abstract: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer within the pillar regions. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: June 2, 2009
    Assignee: Flextronics International USA, Inc.
    Inventors: Berinder P. S. Brar, Wonill Ha
  • Patent number: 7504673
    Abstract: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: March 17, 2009
    Assignee: Flextronics International USA, Inc.
    Inventors: Mariam Gergi Sadaka, Berinder P. S. Brar, Wonill Ha, Chanh Ngoc Minh Nguyen
  • Patent number: 7462891
    Abstract: A semiconductor device having at least one lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a lateral channel above the conductive substrate. The semiconductor device further includes a second contact above the lateral channel. The semiconductor device still further includes an interconnect having a sloped wall that connects the lateral channel to the conductive substrate. The interconnect is operable to provide a low resistance coupling between the first contact and the lateral channel. In a related but alternative embodiment, the first contact is a source contact and the second contact is a drain contact for the semiconductor device.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: December 9, 2008
    Assignee: ColdWatt, Inc.
    Inventors: Berinder P. S. Brar, Wonill Ha, James L. Vorhaus
  • Patent number: 7439556
    Abstract: A substrate driven field effect transistor (FET) and a method of forming the same. In one embodiment, the substrate driven FET includes a substrate having a source contact covering a substantial portion of a bottom surface thereof and a lateral channel above the substrate. The substrate driven FET also includes a drain contact above the lateral channel. The substrate driven FET still further includes a source interconnect that connects the lateral channel to the substrate operable to provide a low resistance coupling between the source contact and the lateral channel.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: October 21, 2008
    Assignee: ColdWatt, Inc.
    Inventors: Berinder P. S. Brar, Peter M. Asbeck
  • Patent number: 7439557
    Abstract: A semiconductor device having a lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a lateral channel above the conductive substrate. The semiconductor device further includes a second contact above the lateral channel. The semiconductor device still further includes an interconnect that connects the lateral channel to the conductive substrate. The interconnect is operable to provide a low resistance coupling between the first contact and the lateral channel.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: October 21, 2008
    Assignee: ColdWatt, Inc.
    Inventors: Berinder P. S. Brar, Wonill Ha
  • Publication number: 20080157122
    Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.
    Type: Application
    Filed: February 26, 2008
    Publication date: July 3, 2008
    Applicant: THE BOEING COMPANY
    Inventor: Berinder P.S. BRAR
  • Publication number: 20080157060
    Abstract: A semiconductor device having multiple lateral channels with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a first lateral channel above the conductive substrate and a second lateral channel above the first lateral channel. The semiconductor device further includes a second contact above the second lateral channel. The semiconductor device still further includes an interconnect that connects the first and second lateral channels to the conductive substrate operable to provide a low resistance coupling between the first contact and the first and second lateral channels.
    Type: Application
    Filed: February 21, 2008
    Publication date: July 3, 2008
    Inventors: Berinder P. S. Brar, Wonill Ha
  • Patent number: 7354820
    Abstract: A method for fabricating an HBT is disclosed, wherein successive emitter, base, collector and sub-collector epitaxial layers are deposited on a substrate, with the substrate being adjacent to the sub-collector layer. The epitaxial layers are etched to provide locations for contact metals and emitter, base and contact metals are deposited on the emitter, base and sub-collector epitaxial layers, respectively. A self-alignment material is deposited on the surface of the substrate around the epitaxial layers and a planarization material is deposited on and covers the top surface of the HBT. The planarization material is then etched so it has a planar surface about the same level as the surface of the self-alignment material and the contact metals protrude from the planar surface. The planar metals are then deposited over the protruding portions of the contact metals.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: April 8, 2008
    Assignee: Teledyne Licensing, LLC
    Inventors: Richard L. Pierson, Jr., James Chingwei Li, Berinder P. S. Brar, John A. Higgins
  • Patent number: 7339209
    Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: March 4, 2008
    Assignee: The Boeing Company
    Inventor: Berinder P. S. Brar