Patents by Inventor Berinder P. S. Brar
Berinder P. S. Brar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8415737Abstract: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.Type: GrantFiled: June 19, 2007Date of Patent: April 9, 2013Assignee: Flextronics International USA, Inc.Inventors: Berinder P. S. Brar, Wonill Ha
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Patent number: 8043910Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.Type: GrantFiled: May 28, 2010Date of Patent: October 25, 2011Assignee: The Boeing CompanyInventor: Berinder P. S. Brar
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Patent number: 7838905Abstract: A semiconductor device having multiple lateral channels with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a first lateral channel above the conductive substrate and a second lateral channel above the first lateral channel. The semiconductor device further includes a second contact above the second lateral channel. The semiconductor device still further includes an interconnect that connects the first and second lateral channels to the conductive substrate operable to provide a low resistance coupling between the first contact and the first and second lateral channels.Type: GrantFiled: February 21, 2008Date of Patent: November 23, 2010Assignee: Flextronics International USA, Inc.Inventors: Berinder P. S. Brar, Wonill Ha
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Publication number: 20100240187Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.Type: ApplicationFiled: May 28, 2010Publication date: September 23, 2010Applicant: THE BOEING COMPANYInventor: Berinder P.S. Brar
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Patent number: 7755106Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.Type: GrantFiled: February 26, 2008Date of Patent: July 13, 2010Assignee: The Boeing CompanyInventor: Berinder P. S. Brar
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Patent number: 7675090Abstract: A semiconductor device and method of forming the same. The semiconductor device includes an epitaxially grown and conductive buffer layer having a contact covering a substantial portion of a bottom surface thereof and a lateral channel above the buffer layer. The semiconductor device also includes another contact above the lateral channel and an interconnect that connects the lateral channel to the buffer layer, operable to provide a low resistance coupling between the contact and the lateral channel.Type: GrantFiled: April 3, 2007Date of Patent: March 9, 2010Assignee: Flextronics International USA, Inc.Inventors: Mariam Gergi Sadaka, Berinder P. S. Brar, Wonill Ha, Chanh Ngoc Minh Nguyen
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Patent number: 7663183Abstract: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer within the pillar regions. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions.Type: GrantFiled: June 19, 2007Date of Patent: February 16, 2010Assignee: Flextronics International USA, Inc.Inventors: Berinder P. S. Brar, Wonill Ha
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Patent number: 7655963Abstract: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.Type: GrantFiled: October 2, 2007Date of Patent: February 2, 2010Assignee: Flextronics International USA, Inc.Inventors: Mariam Gergi Sadaka, Berinder P. S. Brar, Wonill Ha, Chanh Ngoc Minh Nguyen
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Patent number: 7642568Abstract: A semiconductor device including a substrate-driven field-effect transistor with a lateral channel and a parallel-coupled Schottky diode, and a method of forming the same. In one embodiment, the substrate-driven field-effect transistor of the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof, and a lateral channel above the conductive substrate. The substrate-driven field-effect transistor also includes a second contact above the lateral channel and an interconnect that connects the lateral channel to the conductive substrate operable to provide a low resistance coupling between the first contact and the lateral channel. The semiconductor device also includes a Schottky diode parallel-coupled to the substrate-driven field-effect transistor. A first and second terminal of the Schottky diode are couplable to the first and second contacts, respectively, of the substrate drive field-effect transistor.Type: GrantFiled: October 22, 2007Date of Patent: January 5, 2010Assignee: Flextronics International USA, Inc.Inventors: Berinder P. S. Brar, Wonill Ha
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Patent number: 7564074Abstract: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.Type: GrantFiled: October 2, 2007Date of Patent: July 21, 2009Assignee: Flextronics International USA, Inc.Inventors: Mariam Gergi Sadaka, Berinder P. S. Brar, Wonill Ha, Chanh Ngoc Minh Nguyen
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Patent number: 7563713Abstract: A mask layer is applied to a surface of a semiconductor structure or a seed layer deposited on the surface. The mask layer has a submicron width opening with a high aspect ratio that exposes a portion of the surface or seed layer. Conductive material is conformed to the opening, for example by plating, to form a first contact on the surface or seed layer. The mask and the top layer of the semiconductor structure, except for the portion under the first contact, are removed to expose a second layer of the semiconductor structure. An insulating layer is formed along the sidewalls of the first contact and the top layer of the semiconductor structure beneath the first contact. A mask is then applied to the second layer and a second contact is formed by selectively depositing metal only on the portion of the second layer exposed by the opening.Type: GrantFiled: February 23, 2005Date of Patent: July 21, 2009Assignee: Teledyne Scientific & Imaging, LLCInventors: Petra V. Rowell, Miguel E. Urteaga, Richard L. Pierson, Jr., Berinder P. S. Brar
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Patent number: 7541640Abstract: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer within the pillar regions. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions.Type: GrantFiled: June 19, 2007Date of Patent: June 2, 2009Assignee: Flextronics International USA, Inc.Inventors: Berinder P. S. Brar, Wonill Ha
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Patent number: 7504673Abstract: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.Type: GrantFiled: October 2, 2007Date of Patent: March 17, 2009Assignee: Flextronics International USA, Inc.Inventors: Mariam Gergi Sadaka, Berinder P. S. Brar, Wonill Ha, Chanh Ngoc Minh Nguyen
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Patent number: 7462891Abstract: A semiconductor device having at least one lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a lateral channel above the conductive substrate. The semiconductor device further includes a second contact above the lateral channel. The semiconductor device still further includes an interconnect having a sloped wall that connects the lateral channel to the conductive substrate. The interconnect is operable to provide a low resistance coupling between the first contact and the lateral channel. In a related but alternative embodiment, the first contact is a source contact and the second contact is a drain contact for the semiconductor device.Type: GrantFiled: September 27, 2005Date of Patent: December 9, 2008Assignee: ColdWatt, Inc.Inventors: Berinder P. S. Brar, Wonill Ha, James L. Vorhaus
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Patent number: 7439556Abstract: A substrate driven field effect transistor (FET) and a method of forming the same. In one embodiment, the substrate driven FET includes a substrate having a source contact covering a substantial portion of a bottom surface thereof and a lateral channel above the substrate. The substrate driven FET also includes a drain contact above the lateral channel. The substrate driven FET still further includes a source interconnect that connects the lateral channel to the substrate operable to provide a low resistance coupling between the source contact and the lateral channel.Type: GrantFiled: March 29, 2005Date of Patent: October 21, 2008Assignee: ColdWatt, Inc.Inventors: Berinder P. S. Brar, Peter M. Asbeck
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Patent number: 7439557Abstract: A semiconductor device having a lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a lateral channel above the conductive substrate. The semiconductor device further includes a second contact above the lateral channel. The semiconductor device still further includes an interconnect that connects the lateral channel to the conductive substrate. The interconnect is operable to provide a low resistance coupling between the first contact and the lateral channel.Type: GrantFiled: March 29, 2005Date of Patent: October 21, 2008Assignee: ColdWatt, Inc.Inventors: Berinder P. S. Brar, Wonill Ha
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Publication number: 20080157122Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.Type: ApplicationFiled: February 26, 2008Publication date: July 3, 2008Applicant: THE BOEING COMPANYInventor: Berinder P.S. BRAR
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Publication number: 20080157060Abstract: A semiconductor device having multiple lateral channels with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a first lateral channel above the conductive substrate and a second lateral channel above the first lateral channel. The semiconductor device further includes a second contact above the second lateral channel. The semiconductor device still further includes an interconnect that connects the first and second lateral channels to the conductive substrate operable to provide a low resistance coupling between the first contact and the first and second lateral channels.Type: ApplicationFiled: February 21, 2008Publication date: July 3, 2008Inventors: Berinder P. S. Brar, Wonill Ha
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Patent number: 7354820Abstract: A method for fabricating an HBT is disclosed, wherein successive emitter, base, collector and sub-collector epitaxial layers are deposited on a substrate, with the substrate being adjacent to the sub-collector layer. The epitaxial layers are etched to provide locations for contact metals and emitter, base and contact metals are deposited on the emitter, base and sub-collector epitaxial layers, respectively. A self-alignment material is deposited on the surface of the substrate around the epitaxial layers and a planarization material is deposited on and covers the top surface of the HBT. The planarization material is then etched so it has a planar surface about the same level as the surface of the self-alignment material and the contact metals protrude from the planar surface. The planar metals are then deposited over the protruding portions of the contact metals.Type: GrantFiled: September 14, 2005Date of Patent: April 8, 2008Assignee: Teledyne Licensing, LLCInventors: Richard L. Pierson, Jr., James Chingwei Li, Berinder P. S. Brar, John A. Higgins
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Patent number: 7339209Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.Type: GrantFiled: September 7, 2005Date of Patent: March 4, 2008Assignee: The Boeing CompanyInventor: Berinder P. S. Brar