Abstract: A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.

Abstract: A buffer circuit is configured to generate an output signal which is a function of an input signal received by the buffer circuit, the buffer circuit being selectively operative in one of at least two modes in response to a control signal. In a first mode, the buffer circuit is configured to provide a low output impedance, characteristic of a digital buffer. In a second mode, the buffer circuit is configured to limit an output current of the buffer circuit. The control signal is indicative of a level of the output signal of the buffer circuit.

Abstract: A differential buffer circuit includes a current source, a current sink, and a switching circuit connected to the current source at a first node and connected to the current sink at a second node. The switching circuit is operative to selectively control a direction of current flowing through differential outputs of the buffer circuit in response to at least a first control signal. The buffer circuit further includes a common mode detection circuit and a common mode control circuit. The common mode detection circuit is operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage. The common mode control circuit includes a first terminal connected to the current source and a second terminal connected to the current sink. The common mode control circuit is operative to selectively control the output common mode voltage of the buffer circuit as a function of the second control signal.

Abstract: A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.

Abstract: A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.

Abstract: A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal.

Abstract: When a P-channel pass gate transistor is added in parallel to an N-channel pass gate, the resulting circuit improves overvoltage tolerance of an input buffer. A simple bias circuit including two small transistors controls a gate of this P-channel pass gate transistor in such a way that it is turned OFF when an overvoltage is applied, but turned ON when a normal voltage is applied. Another embodiment has two N-channel devices (M12, M13) coupled in series with each other and one of the N-channel devices (M13) being configured in a “turned off” position, by coupling the source and gate terminals to a ground voltage (VSS) and providing the supply voltage (VDD) at the gate terminal of another N-channel device (M12), whereby the device M12 protects the device M13 from overvoltage.

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level includes an input stage for receiving the input signal. The input stage includes at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logical state of the input signal. The latch circuit includes at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp is operatively connected between the input stage and the latch circuit, the voltage clamp being configured to limit a voltage across the input stage based, at least in part, on a control signal presented thereto.

Abstract: A semiconductor resistor circuit having a controllable resistance associated therewith includes a plurality of resistor segments connected in a series and/or parallel configuration. The resistor circuit further includes a plurality of switches controlling connection of respective ones of the resistor segments to the resistor circuit, to thereby selectively control a resistance of the resistor circuit in response to respective control signals presented to the switches. The resistor circuit is selectively controllable in discrete resistance intervals, the resistance intervals being unequal to one another. The resistor segments have resistance values that are selected such that a percentage resistance variation across each of the respective resistance intervals as a function of process, voltage and/or temperature conditions to which the resistor circuit is subjected is substantially the same.

Abstract: A bi-directional buffer includes the capability to turn the current mirror off when the bi-directional buffer is in the receive mode and quickly turn the current mirror on when the bi-directional buffer goes into the transmit mode. This is accomplished in part by a pair of switches included in the current mirror, which are controlled by enable signals. The switches are configured such that the output transistor of the current mirror is turned on when the bi-directional buffer is in the transmit mode, and turned off when the bi-directional buffer is in the receive mode. Further, a pull up circuit may be added to the current mirror to more quickly bring the gate of the output transistor of the current mirror to its conduction threshold voltage.

Abstract: A bidirectional buffer includes the capability to turn the current mirror off when the bidirectional buffer is in the receive mode and quickly turn the current mirror on when the bidirectional buffer goes into the transmit mode. This is accomplished in part by a pair of switches included in the current mirror, which are controlled by enable signals. The switches are configured such that the output transistor of the current mirror is turned on when the bidirectional buffer is in the transmit mode, and turned off when the bidirectional buffer is in the receive mode. Further, a pull up circuit may be added to the current mirror to more quickly bring the gate of the output transistor of the current mirror to its conduction threshold voltage.

Abstract: A voltage blocking circuit is disclosed, useable in a buffer portion of an integrated circuit, for a buffer portion of an IC chip that operates from a power supply different from the power supply that powers the core logic; however, the buffer remains in a high impendence state, regardless of whether or not power is supplied to the core logic.

Abstract: CMOS technology is used to create a controlled output impedance output buffer circuit. An output buffer driver uses buffer circuits having impedance elements with linear characteristics. A control circuit uses a known impedance load to control the impedance of the buffer circuits. The control circuit monitors a known current flowing through the known impedance load to determine whether the output buffer circuit's output impedance needs to be adjusted to match a transmission line's impedance. Adjustments occur when the control circuit generates control signals to turn on or off various buffer circuits (and their impedance elements) contained within the output driver. In doing so, the output buffer circuit ensures that its output impedance will match the impedance of a transmission line over the entire range of output voltages regardless of the variations caused by the manufacturing process, operation temperature and power supply voltage.

Abstract: The input buffer of a low-voltage technology integrated circuit (IC) has a buffer transistor adapted to receive an input signal at the gate of the input buffer. The channel nodes of the input buffer are connected to other circuitry (e.g., the low-voltage bias voltage and a current source). With such an input buffer, the low-voltage circuit can safely receive a relatively high input voltage. As such, the low-voltage circuit can be interfaced to and safely operated in conjunction with relatively high-voltage technology circuitry. In one implementation, IC circuitry of existing 5V technology can be safely used with IC circuitry of a new 2.5V technology having an input buffer of the present invention.

Abstract: An integrated circuit is implemented in a low-voltage technology and has an output driver. The output driver has circuitry adapted to generate an output voltage at an output node (e.g., PAD in FIG. 1) based on an input voltage (e.g., A). Within the output driver, a transistor is configured to limit the drain-to-source voltage drop across another transistor to enable the integrated circuit to tolerate, at its output node, voltages of magnitude up to two times the operating voltage of the integrated circuit. The invention enables low-voltage integrated circuits to be interfaced with other circuitry implemented in a relatively high-voltage technology, without suffering the adverse effects that can otherwise result in the low-voltage circuitry from such interfacing.

Abstract: A differential comparator having a low-offset comparator and two processing paths, each of which receives one of the two primary inputs to the differential comparator and generates one of the two inputs to the low-offset comparator. The output of the low-offset comparator is the output of the differential comparator. Each processing path is capable of (1) generating an offset voltage and (2) turning on and off the generation of that offset voltage. In a preferred embodiment, each processing path has a passive resistor that generates the offset voltage and a pair of shunt transistors that selectively shorts out the passive resistor. The output of the low-offset comparator is connected (either directly or indirectly through an inverter) to the gates of the shunt transistors. The shunt transistors are therefore controlled by the output of the low-offset comparator. In each of two modes of operation, a different one of the passive resistors is "on" while the other passive resistor is "off.

Abstract: CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.

Abstract: An integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to a second node, and a second field effect transistor for protecting the first transistor from voltages applied to the first node and greater than a predetermined nominal voltage. The second transistor includes a drain connected to the second node, a source connected to the first node, and a gate connected to a third node. A constant voltage source is coupled to the third node and supplies a gate voltage to the gate of the second transistor such that a drain-source path of the second transistor does not conduct while voltage applied to the first node is generally less than the gate voltage plus a threshold voltage of the second transistor.

Abstract: The number of active switching elements in a buffer is automatically varied to compensate for variations in the manufacturing process, operating temperature, and power supply voltage. For this purpose, a reference voltage which is proportional to the speed of a switching transistor is applied to an analog-to-digital (A/D) converter. The A/D converter may be implemented with a simple resistor divider and comparators, all of which can be made on-chip. The resistor dividers are chosen such that at worst-case slow conditions all the comparators have high outputs. As the process/temperature/voltage changes, the reference voltage also increases. This successively turns off sections of the switching transistor, thereby slowing down the response of the buffer. Since the control leads are digital, they are not susceptible to noise as they are routed around a chip full of noisy signals. The digital control signals may be latched, and the control circuitry powered down to zero for powersensitive applications.

Abstract: Prior-art high speed TTL-to-CMOS input buffers consume a large amount of power supply current through the input transistors when the input voltage is held at a mid-range level between V.sub.DD and V.sub.SS (e.g., 2.0 volts). The inventive input buffer includes a resistance in series with the p-channel pull-up transistor on the input inverter, in order to limit this current. In addition, to retain high operating speed, a p-channel shunt transistor is placed in parallel with the resistance, and controlled by the buffer output signal. This shunt transistor effectively bypasses the resistance from the circuit when the buffer output goes low, thereby providing high operating speed.