Patents by Inventor Bernard Lee Morris
Bernard Lee Morris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7218169Abstract: A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit.Type: GrantFiled: December 23, 2003Date of Patent: May 15, 2007Assignee: Agere Syatems Inc.Inventors: Dipankar Bhattacharya, Makeshwar Kothandaraman, John Christopher Kriz, Bernard Lee Morris, Jeffrey Jay Nagy, Stefan Allen Siegel
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Patent number: 7138814Abstract: An integrated circuit die comprises an internal signal pad arranged at a location away from a periphery of the die, a peripheral signal pad arranged proximate the periphery of the die, and a switch coupled between the internal signal pad and the peripheral signal pad. The switch is configurable in at least a first state in which the internal signal pad is not operatively connected to the peripheral signal pad, and a second state in which the internal signal pad is operatively connected to the peripheral signal pad, responsive to a control signal having one of respective first and second signal characteristics. The switch is configured in the first state during normal operation of the integrated circuit die, and is configured in the second state to permit test access to the internal signal pad via the peripheral signal pad.Type: GrantFiled: November 21, 2003Date of Patent: November 21, 2006Assignee: Agere Systems Inc.Inventors: Thaddeus John Gabara, Carol Ann Huber, Bernard Lee Morris
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Patent number: 7002372Abstract: A low voltage, 5V tolerant open drain output buffer having moderate current tolerance capabilities is formed with 3.3V technology using a nominal power supply of 2.5V or less. The buffer includes an inverter, a series connection of the current paths of three n-channel FET transistors, and a backgate bias generator. One terminal of the series connection of three transistors is connected to a PAD, and the other terminal of the lower transistor of the series is connected to ground. The bias generator is formed using two p-channel field effect transistors (FETs) that are cross-connected between VDD and the PAD. A gate of a central one of the three transistors is connected to the power supply. An output of the bias generator is connected to a gate of the upper transistor. The inventive buffer may be manufactured using standard 3.3V processes, but functions with a power supply of, e.g., 2.5V or 1.8V.Type: GrantFiled: January 20, 2004Date of Patent: February 21, 2006Assignee: Agere Systems Inc.Inventors: Carol Ann Huber, Bernard Lee Morris, Makeshwar Kothandaraman, Yehuda Smooha
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Patent number: 6977524Abstract: Using at best a 2.5V nominal power supply, 3.3V technology can be used to implement a 5V tolerant open drain output buffer. High voltage and/or current tolerance is achieved with only the 2.5V power supply. A p-channel FET transistor is connected between a power supply and a node, which in turn is connected to a node between two series output FET transistors. The first transistor is connected between the PAD and node, and the second transistor is connected between the node and ground. The gate of the second transistor is driven from another node formed between a series string of a p-channel FET transistor and an n-channel FET transistor. The other side of the first transistor is connected to the power supply, and the other side of the second transistor is connected to ground. The gates of the transistors of the inverter are tied together and driven by an applied signal.Type: GrantFiled: January 20, 2004Date of Patent: December 20, 2005Assignee: Agere Systems Inc.Inventors: Carol Ann Huber, Bernard Lee Morris, Makeshwar Kothandaraman, Yehuda Smooha
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Publication number: 20050156628Abstract: A low voltage, 5V tolerant open drain output buffer having moderate current tolerance capabilities is formed with 3.3V technology using a nominal power supply of 2.5V or less. The buffer includes an inverter, a series connection of the current paths of three n-channel FET transistors, and a backgate bias generator. One terminal of the series connection of three transistors is connected to a PAD, and the other terminal of the lower transistor of the series is connected to ground. The bias generator is formed using two p-channel field effect transistors (FETs) that are cross-connected between VDD and the PAD. A gate of a central one of the three transistors is connected to the power supply. An output of the bias generator is connected to a gate of the upper transistor. The inventive buffer may be manufactured using standard 3.3V processes, but functions with a power supply of, e.g., 2.5V or 1.8V.Type: ApplicationFiled: January 20, 2004Publication date: July 21, 2005Inventors: Carol Ann Huber, Bernard Lee Morris, Makeshwar Kothandaraman, Yehuda Smooha
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Patent number: 6850091Abstract: The present invention provides a bi-directional impedance matching integrated circuit which is couplable through an interface to a channel for signal transmission and reception. The invention includes a first switchable impedance and a second switchable impedance having a respective output impedance and input impedance substantially equal to a channel impedance. An impedance controller is capable of coupling the first switchable impedance to the interface in response to a transmit control signal, coupling the second switchable impedance to the interface in response to a receive control signal, and further capable of uncoupling the first switchable impedance and the second switchable impedance from a power supply and from a ground potential in response to a low power control signal. A mode selector is utilized to provide the transmit control signal, the receive control signal, and the low power control signal.Type: GrantFiled: April 9, 2003Date of Patent: February 1, 2005Assignee: Agere Systems, Inc.Inventor: Bernard Lee Morris
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Publication number: 20040201401Abstract: The present invention provides a bi-directional impedance matching integrated circuit which is couplable through an interface to a channel for signal transmission and reception. The invention includes a first switchable impedance and a second switchable impedance having a respective output impedance and input impedance substantially equal to a channel impedance. An impedance controller is capable of coupling the first switchable impedance to the interface in response to a transmit control signal, coupling the second switchable impedance to the interface in response to a receive control signal, and further capable of uncoupling the first switchable impedance and the second switchable impedance from a power supply and from a ground potential in response to a low power control signal. A mode selector is utilized to provide the transmit control signal, the receive control signal, and the low power control signal.Type: ApplicationFiled: April 9, 2003Publication date: October 14, 2004Applicant: Agere Systems, Inc.Inventor: Bernard Lee Morris
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Patent number: 6774698Abstract: An apparatus is disclosed for translating a lower voltage signal, utilized in a low voltage integrated circuit, to a higher voltage signal suitable for use in a high voltage circuit. The apparatus includes a low voltage transistor assembly capable of operating in response to the lower voltage signal; a voltage regulator which is configured to limit an applied voltage across the low voltage transistor assembly; and a high voltage converter which is responsive to the operation of the low voltage transistor assembly to generate the higher voltage signal. The voltage regulator includes a reference voltage generator and a voltage limiter.Type: GrantFiled: January 30, 2003Date of Patent: August 10, 2004Assignee: Agere Systems Inc.Inventors: Dipankar Bhattacharya, Makeshwar Kothandaraman, John Christopher Kriz, Bernard Lee Morris, Stefan Allen Siegel
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Publication number: 20040150454Abstract: An apparatus is disclosed for translating a lower voltage signal, utilized in a low voltage integrated circuit, to a higher voltage signal suitable for use in a high voltage circuit. The apparatus includes a low voltage transistor assembly capable of operating in response to the lower voltage signal; a voltage regulator which is configured to limit an applied voltage across the low voltage transistor assembly; and a high voltage converter which is responsive to the operation of the low voltage transistor assembly to generate the higher voltage signal. The voltage regulator includes a reference voltage generator and a voltage limiter.Type: ApplicationFiled: January 30, 2003Publication date: August 5, 2004Inventors: Dipankar Bhattacharya, Makeshwar Kothandaraman, John Christopher Kriz, Bernard Lee Morris, Stefan Allen Siegel
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Patent number: 6686789Abstract: A dynamic low power reference circuit includes a reference source for generating a reference voltage and/or a reference current. The reference circuit further includes an activity detector configured to measure an activity level of at least a portion of another circuit coupled to the reference circuit and to generate a control signal representative of the activity level. A controller coupled to the reference source is configured to dynamically change an output impedance of the reference circuit in response to the control signal. The techniques of the present invention thus provide a reference circuit that is capable of dynamically changing an output impedance associated therewith, such that when activity on one or more nodes in the other circuit is detected within a time period, the output impedance of the reference circuit is at a first value which is sufficiently low so as to reduce the likelihood of noise being coupled onto the output of the reference circuit.Type: GrantFiled: March 28, 2002Date of Patent: February 3, 2004Assignee: Agere Systems, Inc.Inventors: Douglas D. Lopata, Bernard Lee Morris
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Patent number: 6631159Abstract: A transceiver comprises a transmitter for transmitting a transmitted signal to a second transceiver via a cable; a first receiver for receiving a received signal via the cable from the receiving device; and a second receiver for detecting a disconnect condition of the cable when the transmitter is transmitting the transmitted signal.Type: GrantFiled: November 10, 1999Date of Patent: October 7, 2003Assignee: Agere Systems, Inc.Inventor: Bernard Lee Morris
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Publication number: 20030184363Abstract: A dynamic low power reference circuit includes a reference source for generating a reference voltage and/or a reference current. The reference circuit further includes an activity detector configured to measure an activity level of at least a portion of another circuit coupled to the reference circuit and to generate a control signal representative of the activity level. A controller coupled to the reference source is configured to dynamically change an output impedance of the reference circuit in response to the control signal. The techniques of the present invention thus provide a reference circuit that is capable of dynamically changing an output impedance associated therewith, such that when activity on one or more nodes in the other circuit is detected within a time period, the output impedance of the reference circuit is at a first value which is sufficiently low so as to reduce the likelihood of noise being coupled onto the output of the reference circuit.Type: ApplicationFiled: March 28, 2002Publication date: October 2, 2003Inventors: Douglas D. Lopata, Bernard Lee Morris
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Patent number: 6433628Abstract: A wafer testable integrated circuit (IC) and method for wafer testing the IC. The IC includes outside row buffer areas, inside row buffer areas having bi-directional buffers, routing circuitry between the buffer areas, and IC logic (including internal IC logic directly accessible through at least one inside row buffer area). The internal logic is indirectly accessible through outside row buffer areas via the routing circuitry coupled between the outside row buffer areas and the inside row buffer areas, and the bi-directional buffers of the inside row buffer areas. The method includes supplying a test signal to a first outside row buffer area, routing the test signal from the first outside row buffer area to internal logic accessible through one or more inside row buffer areas, applying the test signal to the internal logic to generate a resultant signal, routing the resultant signal to a second outside row buffer area, and interpreting the resultant signal at the second outside row buffer area.Type: GrantFiled: May 17, 2001Date of Patent: August 13, 2002Assignee: Agere Systems Guardian Corp.Inventor: Bernard Lee Morris
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Patent number: 6396315Abstract: A voltage clamp for a failsafe buffer used in connection with an electronic device. The voltage clamp clamps a voltage present at the output terminal of the buffer only when the electronic device is powered-on, and present a high impedance when the electronic device is not powered-on. Thus, when an electronic device such as a printer, for example, is connected to a network and the device is in a powered-on state, the voltage at the output terminal of the buffer is clamped to approximately the value of the electronic device power source. When the electronic device is powered-off, a voltage present at the output of the buffer will not clamped by the voltage clamp. Instead, the buffer will present a high impedance to the network and to other electronic devices connected thereto. Consequently, when an electronic device having a failsafe buffer constructed in accordance with the present invention enters an inoperable state due to device failure, power loss, etc.Type: GrantFiled: May 3, 1999Date of Patent: May 28, 2002Assignee: Agere Systems Guardian Corp.Inventor: Bernard Lee Morris
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Patent number: 6259282Abstract: A system and method that compensates for a pull-up resistor coupled to a buffer, when the pull-up resistor has an unknown resistance value. The system includes a buffer and a parameter detector. The buffer receives an input signal at a buffer input, and the buffer generates a buffered signal at a buffer output. The parameter detector measures a parameter at the buffer output when the buffer is in a high impedance output state, and the parameter detector generates a buffer control signal based upon the measured parameter. The buffer responds to the buffer control signal generated by the parameter detector.Type: GrantFiled: August 17, 2000Date of Patent: July 10, 2001Assignee: Agere Systems Guardian Corp.Inventor: Bernard Lee Morris
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Patent number: 6064231Abstract: A low voltage CMOS input buffer protection circuit that is used to protect an input buffer from any high voltage signal (e.g., 5 V) that may appear along a signal bus. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). The circuit includes a CMOS transmission gate and utilizes on-chip generated reference voltages to provide the necessary protection.Type: GrantFiled: April 28, 1998Date of Patent: May 16, 2000Assignee: Lucent Technologies, Inc.Inventors: Makeshwar Kothandaraman, Bernard Lee Morris, Bijit Thakorbhai Patel, Wayne E. Werner
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Patent number: 6064229Abstract: An integrated circuit, voltage translating buffer includes input, intermediate and output circuit stages. Each, circuit stage includes first and second n-FETS and a p-FET connected in series. The first n-FET of the input stage receives a first logic voltage within a low voltage range at its gate terminal. The output stage provides a translated output voltage within a higher voltage range at a circuit node between the second n-FET and the p-FET. Each of the second n-FETS of the three stages is operable to drop sufficient voltage across its conducting channel so as to prevent an excessive voltage drop across the conducting channel of the associated series connected first n-FET. Consequently, low voltage transistors may be used for the n-FETS, such that the buffer circuit can be manufactured with a reduced number of mask levels.Type: GrantFiled: March 26, 1998Date of Patent: May 16, 2000Assignee: Lucent Technologies Inc.Inventor: Bernard Lee Morris
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Patent number: 6014039Abstract: A CMOS high voltage drive output buffer that protects the drive stage from seeing relatively high voltages (e.g., 5 V) during "hot pluggable" conditions (that is, when the reference voltage VDD is not present). A transmission gate and clamping transistors are disposed around the output devices to provide the requisite protection. A backgate bias generator for use with P-channel devices is also disclosed that is capable of withstanding "hot pluggable" conditions.Type: GrantFiled: April 28, 1998Date of Patent: January 11, 2000Assignee: Lucent Technologies Inc.Inventors: Makeshwar Kothandaraman, Bernard Lee Morris, Bijit Thakorbhai Patel, Wayne E. Werner
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Patent number: 5973530Abstract: An integrated, low power bus holder circuit implemented in low voltage technology is capable of interfacing with a relatively high voltage bus. In an illustrative embodiment, the bus holder circuit includes a first inverter for inverting a logic voltage present on a data bus and a second inverter for inverting the output of the first inverter. The second inverter is comprised of a series string of first and second pFETS and first and second nFETS, with the gates of the first pFET and first nFET coupled to the output of the first inverter. The data bus is coupled to a first circuit node between the second nFET and second pFET, and the bus logic level is maintained thereat. A third pFET is coupled to the second inverter and conducts current when a high logic voltage is present on the bus. A resistance device is coupled between a drain of the third pFET and a point of low reference potential.Type: GrantFiled: May 29, 1998Date of Patent: October 26, 1999Assignee: Lucent Technologies Inc.Inventors: Bernard Lee Morris, Bijit Thakorbhai Patel
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Patent number: 5963083Abstract: A CMOS voltage generator for providing a reference voltage VDD2 that will track the low level power supply voltage VDD (approximately 3.0V-3.6V) as long as the power supply is present. When VDD is not present (defined as at "hot pluggable" condition), the voltage generator is configured to maintain a "protection" output voltage less than the relatively high voltage (approximately 5V) that may appear along a circuit signal bus. In particular, the circuit includes at least a pair of diode-connected N-channel devices disposed between the signal bus line and the output voltage terminal to provide the necessary protection.Type: GrantFiled: April 28, 1998Date of Patent: October 5, 1999Assignee: Lucent Technologies, Inc.Inventors: Makeshwar Kothandaraman, Bernard Lee Morris, Bijit Thakorbhai Patel, Wayne E. Werner