Patents by Inventor Bernard Ramanadin
Bernard Ramanadin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8832471Abstract: A system comprises a central processing unit (10), an interconnection bus (1), and a plurality of functional modules (11-15, 21) corresponding to distinct power domains and able to communicate with each other and/or with the central processing unit via the bus. At least one of the power domains, and is configured to be substituted for a slave functional module (21) of the power domain when the power to the power domain is turned off by the central processing unit. It signals an error in response to any request of a transaction that is in progress between the slave functional module and a master functional module at the moment the power is turned off.Type: GrantFiled: July 23, 2010Date of Patent: September 9, 2014Assignee: ST-Ericsson SAInventors: Bernard Ramanadin, Tedder Meng, Wei Tao Wang, Robert (Yanxim) Chen, Gabriel Duffy
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Publication number: 20120137145Abstract: A system comprises a central processing unit (10), an interconnection bus (1), and a plurality of functional modules (11-15, 21) corresponding to distinct power domains and able to communicate with each other and/or with the central processing unit via the bus. At least one of the power domains, and is configured to be substituted for a slave functional module (21) of the power domain when the power to the power domain is turned off by the central processing unit. It signals an error in response to any request of a transaction that is in progress between the slave functional module and a master functional module at the moment the power is turned off.Type: ApplicationFiled: July 23, 2010Publication date: May 31, 2012Inventors: Bernard Ramanadin, Tedder Meng, Wei Tao Wang, Robert (Yanxim) Chen, Gabriel Duffy
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Patent number: 7016988Abstract: An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N output signals. Only one data input of the enable register receives an enable signal. In this way, the propagation time at the input of the buffer register is reduced.Type: GrantFiled: November 4, 2003Date of Patent: March 21, 2006Assignee: STMicroelectronics, S.A.Inventor: Bernard Ramanadin
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Patent number: 6859891Abstract: An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.Type: GrantFiled: October 1, 1999Date of Patent: February 22, 2005Assignee: STMicroelectronics LimitedInventors: David Alan Edwards, Margaret Rose Gearty, Bernard Ramanadin, Anthony Willis Rich
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Publication number: 20040193836Abstract: A resynchronization module for use in an electronic system comprising a system bus comprises pipeline means of for pipelining the transactions intended for and/or originating from the associated functional module. The pipeline means comprise a first buffer circuit and at least one second buffer circuit, which are connected in parallel, and are each, adapted for storing transaction data of a specific transaction.Type: ApplicationFiled: November 4, 2003Publication date: September 30, 2004Applicant: STMICROELECTRONICS S.A.Inventor: Bernard Ramanadin
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Publication number: 20040174752Abstract: An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N output signals. Only one data input of the enable register receives an enable signal. In this way, the propagation time at the input of the buffer register is reduced.Type: ApplicationFiled: November 4, 2003Publication date: September 9, 2004Applicant: STMICROELECTRONICS S.A.Inventor: Bernard Ramanadin
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Patent number: 6779145Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.Type: GrantFiled: October 1, 1999Date of Patent: August 17, 2004Assignee: STMicroelectronics LimitedInventors: David A. Edwards, Stephen James Wright, Bernard Ramanadin
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Patent number: 6701405Abstract: A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central processing unit(s) and peripherals. A direct memory access controller (DMAC) is provided with a peripheral-independent interface coupled to the system bus and communicates with the system bus using system bus defined transactions. The DMAC comprises a set of registers. A central processing unit (CPU) configures teh DMAC by loading values into the DMAC registers. The configured DMAC issues an enable signal to a selected system component identified in the DMAC registers. A peripheral request interface is associated with the selected system components and communicates with the system bus using the system bus defined transactions. The selected system component asserts a request signal to the DMAC.Type: GrantFiled: October 1, 1999Date of Patent: March 2, 2004Assignee: Hitachi, Ltd.Inventors: Vijaya Pratap Adusumilli, Bernard Ramanadin, Atsushi Hasegawa, Shinichi Yoshioka, Takanobu Naruse
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Patent number: 6601189Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.Type: GrantFiled: October 1, 1999Date of Patent: July 29, 2003Assignee: STMicroelectronics LimitedInventors: David Alan Edwards, Anthony Willis Rich, Bernard Ramanadin
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Patent number: 6590907Abstract: An integrated circuit which has a packet router to which a plurality of functional modules are connected by respective ports is described. One of the ports acts as a socket port for an expansion socket. The expansion socket provides a plurality of additional expansion ports to which additional functional modules can optionally be connected. All the ports connected to the packet router, including the expansion socket port, preferably lie in a common address space for the integrated circuit.Type: GrantFiled: October 1, 1999Date of Patent: July 8, 2003Assignee: STMicroelectronics Ltd.Inventors: Andrew M. Jones, John A. Carey, Bernard Ramanadin, Atsushi Hasegawa
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Publication number: 20030115506Abstract: An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.Type: ApplicationFiled: October 1, 1999Publication date: June 19, 2003Inventors: DAVID ALAN EDWARDS, MARGARET ROSE GEARTY, BERNARD RAMANADIN, ANTHONY WILLIS RICH
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Patent number: 6530047Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.Type: GrantFiled: October 1, 1999Date of Patent: March 4, 2003Assignee: STMicroelectronics LimitedInventors: David Alan Edwards, Stephen James Wright, Bernard Ramanadin
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Patent number: 6349371Abstract: In a system comprising an interconnect and a plurality of modules connected to the interconnect, a circuit for controlling which of said modules is able to put information onto said interconnect, said circuit comprising a store which stores status information for each module, said status information defining if the respective module is permitted to put information on said interconnect.Type: GrantFiled: October 1, 1999Date of Patent: February 19, 2002Assignee: STMicroelectronics Ltd.Inventors: Bernard Ramanadin, David A. Edwards, Andrew M. Jones, John A. Carey, Anthony W. Rich
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Patent number: 6175257Abstract: An integrated circuit includes a master circuit operating at a first frequency for controlling slave circuits operating at a second frequency. The integrated circuit uses registers for eliminating difficulties arising from different and independent frequencies of the master and slave circuits.Type: GrantFiled: February 19, 1999Date of Patent: January 16, 2001Assignee: STMicroelectronics S.A.Inventor: M. Bernard Ramanadin
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Patent number: 6091664Abstract: A substitution circuit for elementary flip-flop circuits is provided to enable the automatic transposition of a flip-flop circuit whose clock signal comes from a combinational logic circuit. To do this, an over-sampled internal clock signal is used along with a synchronous pulse generator to validate the data.Type: GrantFiled: June 3, 1999Date of Patent: July 18, 2000Assignee: STMicroelectronics S.A.Inventor: Bernard Ramanadin